channel_config_set_chain_to() function

Pointer to channel configuration object

Channel to trigger when this channel completes.

Configure all DMA parameters and optionally start transfer

Select a transfer request signal in a channel configuration object The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ 0x3b -> Select Timer 0 as TREQ 0x3c -> Select Timer 1 as TREQ 0x3d -> Select Timer 2 as TREQ (Optional) 0x3e -> Select Timer 3 as TREQ (Optional) 0x3f -> Permanent request, for unpaced transfers.

Set the size of each DMA bus transfer in a channel configuration object Set the size of each bus transfer (byte/halfword/word). The read and write addresses advance by the specific amount (1/2/4 bytes) with each transfer.

Set DMA channel read increment in a channel configuration object

Set DMA channel write increment in a channel configuration object

Set IRQ quiet mode in a channel configuration object In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

Set address wrapping parameters in a channel configuration object Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible (size_bits from 1 - 15) 0x0 -> No wrapping.

Enable access to channel by sniff hardware in a channel configuration object Sniff HW must be enabled and have this channel selected.

Get the raw configuration register from a channel configuration

Set DMA byte swapping config in a channel configuration object No effect for byte data, for halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse their order.

Set the channel priority in a channel configuration object When true, gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

Enable/Disable the DMA channel in a channel configuration object When false, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

Set a channel configuration