spi_flash_chip_generic_config_host_io_mode() function

Pointer to SPI flash chip to use. If NULL, esp_flash_default_chip is substituted.

Special rules to configure io mode, (i.e. Whether 32 bit commands will be used (Currently only W25Q256 and GD25Q256 are supported))

Erase a region of the flash chip Sector size is specifyed in chip->drv->sector_size field (typically 4096 bytes.) ESP_ERR_INVALID_ARG will be returned if the start & length are not a multiple of this size. Erase is performed using block (multi-sector) erases where possible (block size is specified in chip->drv->block_erase_size field, typically 65536 bytes). Remaining sectors are erased using individual sector erase commands.

Generic reset function

Handle explicit yield requests

Perform a write using on-chip flash encryption. Not implemented yet.

Read flash status via the RDSR command and wait for bit 0 (write in progress bit) to be cleared.

Erase chip by using the generic erase chip command.

Perform a generic write. Split the write buffer into page program operations, and call chip->chip_drv->page-program() for each.

Send commands to read one of the reg of the chip

Send the write enable or write disable command and verify the expected bit (1) in the status register is set.

Check whether WEL (write enable latch) bit is set in the Status Register read from RDSR.

Detect flash size based on flash ID.

Read data from the SPI flash chip There are no alignment constraints on buffer, address or length.

Read from flash by using a read command that matches the programmed read mode.

Setup for flash suspend command configuration.

Check if appropriate chip driver is set.

Generic size detection function Tries to detect the size of chip by using the lower 4 bits of the chip->drv->read_id result = N, and assuming size is 2 ^ N.

Erase sector by using the generic sector erase command.

Erase block by the generic 64KB block erase command

Perform a page program using the page program command.

Read the chip unique ID.

Utility function for set_read_mode chip_drv function. If required, set and check the QE bit in the flash chip to enable the QIO/QOUT mode. Most chip QE enable follows a common pattern, though commands to read/write the status register may be different, as well as the position of QE bit. Registers to actually do Quad transtions and command to be sent in reading should also be configured via spi_flash_chip_generic_config_host_io_mode(). Note that the bit length and qe position of wrsr_func, rdsr_func and qe_sr_bit should be consistent.

Write data to the SPI flash chip There are no alignment constraints on buffer, address or length.

Get whether the Quad Enable (QE) is set.

Use RDSR (05H) to read bit 7-0 of the SR.

Set the specified SPI read mode according to the data in the chip context. Set quad enable status register bit if needed.

Utility Functions Returns true if chip is configured for Quad I/O or Quad Fast Read.

Read and decrypt data from the SPI flash chip using on-chip hardware flash encryption

Detect flash size based on flash ID.

Use RDSR2 (35H) to read bit 15-8 of the SR.

Utility functions

Encrypted and write data to the SPI flash chip using on-chip hardware flash encryption

Initialize OS-level functions for the main flash chip.

Use WRSR (01H) to write bit 15-0 of the SR.

Use RDSR2 (35H) to read bit 15-8 of the SR, and RDSR (05H) to read bit 7-0.

Use WRSR (01H) to write bit 7-0 of the SR.

Read the chip unique ID unsupported function.

Register a partition on an external flash chip This API allows designating certain areas of external flash chips (identified by the esp_flash_t structure) as partitions. This allows using them with components which access SPI flash through the esp_partition API.

Initialise SPI flash chip interface. This function must be called before any other API functions are called for this chip.

Read flash ID via the common "RDID" SPI flash command. ID is a 24-bit value. Lower 16 bits of 'id' are the chip ID, upper 8 bits are the manufacturer ID.

Initialize main flash

Initialize OS-level functions for a specific chip.

Deinitialize OS-level functions

Disable OS-level functions for the main flash chip during special phases (e.g. coredump)

Generic probe function

Use WRSR2 (31H) to write bit 15-8 of the SR.

ISSI SPI flash chip_drv, uses all the above functions for its operations. In default autodetection, this is used as a catchall if a more specific chip_drv is not found.

GD (GigaDevice) SPI flash chip_drv, uses all the above functions for its operations. In default autodetection, this is used as a catchall if a more specific chip_drv is not found. Note that this is for GD chips with product ID 40H (GD25Q) and 60H (GD25LQ). The chip diver uses different commands to write the SR2 register according to the chip ID. For GD25Q40 - GD25Q16 chips, and GD25LQ chips, WRSR (01H) command is used; while WRSR2 (31H) is used for GD25Q32 - GD25Q127 chips.

Add a SPI Flash device onto the SPI bus. The bus should be already initialized by ``spi_bus_initialization``.

Remove a SPI Flash device from the SPI bus.

Read flash unique ID via the common "RDUID" SPI flash command. ID is a 64-bit value.

Erase flash chip contents

Read if the entire chip is write protected

Set write protection for the SPI flash chip Some SPI flash chips may require a power cycle before write protect status can be cleared. Otherwise, write protection can be removed via a follow-up call to this function.

Read the list of individually protectable regions of this SPI flash chip.

Detect if a region of the SPI flash chip is protected

Update the protected status for a region of the SPI flash chip

Set or clear dangerous write protection check on the flash chip. This function sets the runtime option to allow or disallow writing to dangerous areas such as the bootloader and partition table. If CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set, this function allows the caller to toggle the protection for specific areas. If CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is set, there is no protection check in the system, and this function does nothing.