SourceVu will show references to spi_bus_config_t from the following samples and libraries:
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spi_bus_config_t struct
This is a configuration structure for a SPI bus. You can use this structure to specify the GPIO pins of the bus. Normally, the driver will use the GPIO matrix to route the signals. An exception is made when all signals either can be routed through the IO_MUX or are -1. In that case, the IO_MUX is used. On ESP32, using GPIO matrix will bring about 25ns of input delay, which may cause incorrect read for >40MHz speeds.
Syntax
typedef struct
{
union {
int mosi_io_num;
int data0_io_num;
};
union {
int miso_io_num;
int data1_io_num;
};
int sclk_io_num;
union {
int quadwp_io_num;
int data2_io_num;
};
union {
int quadhd_io_num;
int data3_io_num;
};
int data4_io_num;
int data5_io_num;
int data6_io_num;
int data7_io_num;
bool data_io_default_level;
int max_transfer_sz;
uint32_t flags;
esp_intr_cpu_affinity_t isr_cpu_id;
int intr_flags;
} spi_bus_config_t;
Fields
Field
Declared as
Description
uint32_t
int
Interrupt flag for the bus to set the priority, and IRAM attribute, see ``esp_intr_alloc.h``. Note that the EDGE, INTRDISABLED attribute are ignored by the driver. Note that if ESP_INTR_FLAG_IRAM is set, ALL the callbacks of the driver, and their callee functions, should be put in the IRAM.
Related Functions
Found 9 other functions taking a spi_bus_config_t
argument:
Function
Description
Initialize a SPI bus @warning SPI0/1 is not supported @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in DMA-capable memory. @warning The ISR of SPI is always executed on the core which calls this function. Never starve the ISR on this core or the SPI transactions will not be handled.
Free the IO used by a SPI peripheral
Connect a SPI peripheral to GPIO pins This routine is used to connect a SPI peripheral to the IO-pads and DMA channel given in the arguments. Depending on the IO-pads requested, the routing is done either using the IO_mux or using the GPIO matrix.
Initialize a SPI bus as a slave interface @warning SPI0/1 is not supported @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in DMA-capable memory. @warning The ISR of SPI is always executed on the core which calls this function. Never starve the ISR on this core or the SPI transactions will not be handled.
Initialize the SPI Slave HD driver.