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rtc_cntl_dev_s struct
Syntax
struct rtc_cntl_dev_s
{
union {
struct {
uint32_t sw_stall_appcpu_c0: 2;
uint32_t sw_stall_procpu_c0: 2;
uint32_t sw_appcpu_rst: 1;
uint32_t sw_procpu_rst: 1;
uint32_t bb_i2c_force_pd: 1;
uint32_t bb_i2c_force_pu: 1;
uint32_t bbpll_i2c_force_pd: 1;
uint32_t bbpll_i2c_force_pu: 1;
uint32_t bbpll_force_pd: 1;
uint32_t bbpll_force_pu: 1;
uint32_t xtl_force_pd: 1;
uint32_t xtl_force_pu: 1;
uint32_t bias_sleep_folw_8m: 1;
uint32_t bias_force_sleep: 1;
uint32_t bias_force_nosleep: 1;
uint32_t bias_i2c_folw_8m: 1;
uint32_t bias_i2c_force_pd: 1;
uint32_t bias_i2c_force_pu: 1;
uint32_t bias_core_folw_8m: 1;
uint32_t bias_core_force_pd: 1;
uint32_t bias_core_force_pu: 1;
uint32_t xtl_force_iso: 1;
uint32_t pll_force_iso: 1;
uint32_t analog_force_iso: 1;
uint32_t xtl_force_noiso: 1;
uint32_t pll_force_noiso: 1;
uint32_t analog_force_noiso: 1;
uint32_t dg_wrap_force_rst: 1;
uint32_t dg_wrap_force_norst: 1;
uint32_t sw_sys_rst: 1;
};
uint32_t val;
} options0;
uint32_t slp_timer0;
union {
struct {
uint32_t slp_val_hi: 16;
uint32_t main_timer_alarm_en: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} slp_timer1;
union {
struct {
uint32_t reserved0: 30;
uint32_t valid: 1;
uint32_t update: 1;
};
uint32_t val;
} time_update;
uint32_t time0;
union {
struct {
uint32_t time_hi:16;
uint32_t reserved16: 16;
};
uint32_t val;
} time1;
union {
struct {
uint32_t reserved0: 20;
uint32_t touch_wakeup_force_en: 1;
uint32_t ulp_cp_wakeup_force_en: 1;
uint32_t apb2rtc_bridge_sel: 1;
uint32_t touch_slp_timer_en: 1;
uint32_t ulp_cp_slp_timer_en: 1;
uint32_t reserved25: 3;
uint32_t sdio_active_ind: 1;
uint32_t slp_wakeup: 1;
uint32_t slp_reject: 1;
uint32_t sleep_en: 1;
};
uint32_t val;
} state0;
union {
struct {
uint32_t cpu_stall_en: 1;
uint32_t cpu_stall_wait: 5;
uint32_t ck8m_wait: 8;
uint32_t xtl_buf_wait: 10;
uint32_t pll_buf_wait: 8;
};
uint32_t val;
} timer1;
union {
struct {
uint32_t reserved0: 15;
uint32_t ulpcp_touch_start_wait: 9;
uint32_t min_time_ck8m_off: 8;
};
uint32_t val;
} timer2;
union {
struct {
uint32_t wifi_wait_timer: 9;
uint32_t wifi_powerup_timer: 7;
uint32_t rom_ram_wait_timer: 9;
uint32_t rom_ram_powerup_timer: 7;
};
uint32_t val;
} timer3;
union {
struct {
uint32_t rtc_wait_timer: 9;
uint32_t rtc_powerup_timer: 7;
uint32_t dg_wrap_wait_timer: 9;
uint32_t dg_wrap_powerup_timer: 7;
};
uint32_t val;
} timer4;
union {
struct {
uint32_t ulp_cp_subtimer_prediv: 8;
uint32_t min_slp_val: 8;
uint32_t rtcmem_wait_timer: 9;
uint32_t rtcmem_powerup_timer: 7;
};
uint32_t val;
} timer5;
union {
struct {
uint32_t reserved0: 23;
uint32_t plla_force_pd: 1;
uint32_t plla_force_pu: 1;
uint32_t bbpll_cal_slp_start: 1;
uint32_t pvtmon_pu: 1;
uint32_t txrf_i2c_pu: 1;
uint32_t rfrx_pbus_pu: 1;
uint32_t reserved29: 1;
uint32_t ckgen_i2c_pu: 1;
uint32_t pll_i2c_pu: 1;
};
uint32_t val;
} ana_conf;
union {
struct {
uint32_t reset_cause_procpu: 6;
uint32_t reset_cause_appcpu: 6;
uint32_t appcpu_stat_vector_sel: 1;
uint32_t procpu_stat_vector_sel: 1;
uint32_t reserved14: 18;
};
uint32_t val;
} reset_state;
union {
struct {
uint32_t wakeup_cause: 11;
uint32_t rtc_wakeup_ena: 11;
uint32_t gpio_wakeup_filter: 1;
uint32_t reserved23: 9;
};
uint32_t val;
} wakeup_state;
union {
struct {
uint32_t slp_wakeup: 1;
uint32_t slp_reject: 1;
uint32_t sdio_idle: 1;
uint32_t rtc_wdt: 1;
uint32_t rtc_time_valid: 1;
uint32_t rtc_ulp_cp: 1;
uint32_t rtc_touch: 1;
uint32_t rtc_brown_out: 1;
uint32_t rtc_main_timer: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t slp_wakeup: 1;
uint32_t slp_reject: 1;
uint32_t sdio_idle: 1;
uint32_t rtc_wdt: 1;
uint32_t rtc_time_valid: 1;
uint32_t rtc_ulp_cp: 1;
uint32_t rtc_touch: 1;
uint32_t rtc_brown_out: 1;
uint32_t rtc_main_timer: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t slp_wakeup: 1;
uint32_t slp_reject: 1;
uint32_t sdio_idle: 1;
uint32_t rtc_wdt: 1;
uint32_t rtc_time_valid: 1;
uint32_t rtc_sar: 1;
uint32_t rtc_touch: 1;
uint32_t rtc_brown_out: 1;
uint32_t rtc_main_timer: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t slp_wakeup: 1;
uint32_t slp_reject: 1;
uint32_t sdio_idle: 1;
uint32_t rtc_wdt: 1;
uint32_t rtc_time_valid: 1;
uint32_t rtc_sar: 1;
uint32_t rtc_touch: 1;
uint32_t rtc_brown_out: 1;
uint32_t rtc_main_timer: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} int_clr;
uint32_t rtc_store0;
uint32_t rtc_store1;
uint32_t rtc_store2;
uint32_t rtc_store3;
union {
struct {
uint32_t reserved0: 30;
uint32_t ctr_lv: 1;
uint32_t ctr_en: 1;
};
uint32_t val;
} ext_xtl_conf;
union {
struct {
uint32_t reserved0: 30;
uint32_t wakeup0_lv: 1;
uint32_t wakeup1_lv: 1;
};
uint32_t val;
} ext_wakeup_conf;
union {
struct {
uint32_t reserved0: 24;
uint32_t gpio_reject_en: 1;
uint32_t sdio_reject_en: 1;
uint32_t light_slp_reject_en: 1;
uint32_t deep_slp_reject_en: 1;
uint32_t reject_cause: 4;
};
uint32_t val;
} slp_reject_conf;
union {
struct {
uint32_t reserved0: 29;
uint32_t cpusel_conf: 1;
uint32_t cpuperiod_sel: 2;
};
uint32_t val;
} cpu_period_conf;
union {
struct {
uint32_t reserved0: 22;
uint32_t sdio_act_dnum:10;
};
uint32_t val;
} sdio_act_conf;
union {
struct {
uint32_t reserved0: 4;
uint32_t ck8m_div: 2;
uint32_t enb_ck8m: 1;
uint32_t enb_ck8m_div: 1;
uint32_t dig_xtal32k_en: 1;
uint32_t dig_clk8m_d256_en: 1;
uint32_t dig_clk8m_en: 1;
uint32_t ck8m_dfreq_force: 1;
uint32_t ck8m_div_sel: 3;
uint32_t xtal_force_nogating: 1;
uint32_t ck8m_force_nogating: 1;
uint32_t ck8m_dfreq: 8;
uint32_t ck8m_force_pd: 1;
uint32_t ck8m_force_pu: 1;
uint32_t soc_clk_sel: 2;
uint32_t fast_clk_rtc_sel: 1;
uint32_t ana_clk_rtc_sel: 2;
};
uint32_t val;
} clk_conf;
union {
struct {
uint32_t reserved0: 21;
uint32_t sdio_pd_en: 1;
uint32_t sdio_force: 1;
uint32_t sdio_tieh: 1;
uint32_t reg1p8_ready: 1;
uint32_t drefl_sdio: 2;
uint32_t drefm_sdio: 2;
uint32_t drefh_sdio: 2;
uint32_t xpd_sdio: 1;
};
uint32_t val;
} sdio_conf;
union {
struct {
uint32_t reserved0: 24;
uint32_t dbg_atten: 2;
uint32_t enb_sck_xtal: 1;
uint32_t inc_heartbeat_refresh: 1;
uint32_t dec_heartbeat_period: 1;
uint32_t inc_heartbeat_period: 1;
uint32_t dec_heartbeat_width: 1;
uint32_t rst_bias_i2c: 1;
};
uint32_t val;
} bias_conf;
union {
struct {
uint32_t reserved0: 7;
uint32_t sck_dcap_force: 1;
uint32_t dig_dbias_slp: 3;
uint32_t dig_dbias_wak: 3;
uint32_t sck_dcap: 8;
uint32_t rtc_dbias_slp: 3;
uint32_t rtc_dbias_wak: 3;
uint32_t rtc_dboost_force_pd: 1;
uint32_t rtc_dboost_force_pu: 1;
uint32_t rtc_force_pd: 1;
uint32_t rtc_force_pu: 1;
};
uint32_t val;
} rtc;
union {
struct {
uint32_t fastmem_force_noiso: 1;
uint32_t fastmem_force_iso: 1;
uint32_t slowmem_force_noiso: 1;
uint32_t slowmem_force_iso: 1;
uint32_t rtc_force_iso: 1;
uint32_t force_noiso: 1;
uint32_t fastmem_folw_cpu: 1;
uint32_t fastmem_force_lpd: 1;
uint32_t fastmem_force_lpu: 1;
uint32_t slowmem_folw_cpu: 1;
uint32_t slowmem_force_lpd: 1;
uint32_t slowmem_force_lpu: 1;
uint32_t fastmem_force_pd: 1;
uint32_t fastmem_force_pu: 1;
uint32_t fastmem_pd_en: 1;
uint32_t slowmem_force_pd: 1;
uint32_t slowmem_force_pu: 1;
uint32_t slowmem_pd_en: 1;
uint32_t pwc_force_pd: 1;
uint32_t pwc_force_pu: 1;
uint32_t pd_en: 1;
uint32_t reserved21: 11;
};
uint32_t val;
} rtc_pwc;
union {
struct {
uint32_t reserved0: 3;
uint32_t lslp_mem_force_pd: 1;
uint32_t lslp_mem_force_pu: 1;
uint32_t rom0_force_pd: 1;
uint32_t rom0_force_pu: 1;
uint32_t inter_ram0_force_pd: 1;
uint32_t inter_ram0_force_pu: 1;
uint32_t inter_ram1_force_pd: 1;
uint32_t inter_ram1_force_pu: 1;
uint32_t inter_ram2_force_pd: 1;
uint32_t inter_ram2_force_pu: 1;
uint32_t inter_ram3_force_pd: 1;
uint32_t inter_ram3_force_pu: 1;
uint32_t inter_ram4_force_pd: 1;
uint32_t inter_ram4_force_pu: 1;
uint32_t wifi_force_pd: 1;
uint32_t wifi_force_pu: 1;
uint32_t dg_wrap_force_pd: 1;
uint32_t dg_wrap_force_pu: 1;
uint32_t reserved21: 3;
uint32_t rom0_pd_en: 1;
uint32_t inter_ram0_pd_en: 1;
uint32_t inter_ram1_pd_en: 1;
uint32_t inter_ram2_pd_en: 1;
uint32_t inter_ram3_pd_en: 1;
uint32_t inter_ram4_pd_en: 1;
uint32_t wifi_pd_en: 1;
uint32_t dg_wrap_pd_en: 1;
};
uint32_t val;
} dig_pwc;
union {
struct {
uint32_t reserved0: 7;
uint32_t dig_iso_force_off: 1;
uint32_t dig_iso_force_on: 1;
uint32_t dg_pad_autohold: 1;
uint32_t clr_dg_pad_autohold: 1;
uint32_t dg_pad_autohold_en: 1;
uint32_t dg_pad_force_noiso: 1;
uint32_t dg_pad_force_iso: 1;
uint32_t dg_pad_force_unhold: 1;
uint32_t dg_pad_force_hold: 1;
uint32_t rom0_force_iso: 1;
uint32_t rom0_force_noiso: 1;
uint32_t inter_ram0_force_iso: 1;
uint32_t inter_ram0_force_noiso: 1;
uint32_t inter_ram1_force_iso: 1;
uint32_t inter_ram1_force_noiso: 1;
uint32_t inter_ram2_force_iso: 1;
uint32_t inter_ram2_force_noiso: 1;
uint32_t inter_ram3_force_iso: 1;
uint32_t inter_ram3_force_noiso: 1;
uint32_t inter_ram4_force_iso: 1;
uint32_t inter_ram4_force_noiso: 1;
uint32_t wifi_force_iso: 1;
uint32_t wifi_force_noiso: 1;
uint32_t dg_wrap_force_iso: 1;
uint32_t dg_wrap_force_noiso: 1;
};
uint32_t val;
} dig_iso;
union {
struct {
uint32_t reserved0: 7;
uint32_t pause_in_slp: 1;
uint32_t appcpu_reset_en: 1;
uint32_t procpu_reset_en: 1;
uint32_t flashboot_mod_en: 1;
uint32_t sys_reset_length: 3;
uint32_t cpu_reset_length: 3;
uint32_t level_int_en: 1;
uint32_t edge_int_en: 1;
uint32_t stg3: 3;
uint32_t stg2: 3;
uint32_t stg1: 3;
uint32_t stg0: 3;
uint32_t en: 1;
};
uint32_t val;
} wdt_config0;
uint32_t wdt_config1;
uint32_t wdt_config2;
uint32_t wdt_config3;
uint32_t wdt_config4;
union {
struct {
uint32_t reserved0: 31;
uint32_t feed: 1;
};
uint32_t val;
} wdt_feed;
uint32_t wdt_wprotect;
union {
struct {
uint32_t reserved0: 29;
uint32_t ent_rtc: 1;
uint32_t dtest_rtc: 2;
};
uint32_t val;
} test_mux;
union {
struct {
uint32_t reserved0: 20;
uint32_t appcpu_c1: 6;
uint32_t procpu_c1: 6;
};
uint32_t val;
} sw_cpu_stall;
uint32_t store4;
uint32_t store5;
uint32_t store6;
uint32_t store7;
uint32_t diag0;
uint32_t diag1;
union {
struct {
uint32_t adc1_hold_force: 1;
uint32_t adc2_hold_force: 1;
uint32_t pdac1_hold_force: 1;
uint32_t pdac2_hold_force: 1;
uint32_t sense1_hold_force: 1;
uint32_t sense2_hold_force: 1;
uint32_t sense3_hold_force: 1;
uint32_t sense4_hold_force: 1;
uint32_t touch_pad0_hold_force: 1;
uint32_t touch_pad1_hold_force: 1;
uint32_t touch_pad2_hold_force: 1;
uint32_t touch_pad3_hold_force: 1;
uint32_t touch_pad4_hold_force: 1;
uint32_t touch_pad5_hold_force: 1;
uint32_t touch_pad6_hold_force: 1;
uint32_t touch_pad7_hold_force: 1;
uint32_t x32p_hold_force: 1;
uint32_t x32n_hold_force: 1;
uint32_t reserved18: 14;
};
uint32_t val;
} hold_force;
union {
struct {
uint32_t ext_wakeup1_sel: 18;
uint32_t ext_wakeup1_status_clr: 1;
uint32_t reserved19: 13;
};
uint32_t val;
} ext_wakeup1;
union {
struct {
uint32_t ext_wakeup1_status:18;
uint32_t reserved18: 14;
};
uint32_t val;
} ext_wakeup1_status;
union {
struct {
uint32_t reserved0: 14;
uint32_t close_flash_ena: 1;
uint32_t pd_rf_ena: 1;
uint32_t rst_wait: 10;
uint32_t rst_ena: 1;
uint32_t thres: 3;
uint32_t ena: 1;
uint32_t det: 1;
};
uint32_t val;
} brown_out;
uint32_t reserved_39;
uint32_t reserved_3d;
uint32_t reserved_41;
uint32_t reserved_45;
uint32_t reserved_49;
uint32_t reserved_4d;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
} date;
};
Fields
Field
Declared as
union {
struct {
uint32_t cpu_stall_en: 1;
uint32_t cpu_stall_wait: 5;
uint32_t ck8m_wait: 8;
uint32_t xtl_buf_wait: 10;
uint32_t pll_buf_wait: 8;
};
uint32_t val;
}
union {
struct {
uint32_t reserved0: 15;
uint32_t ulpcp_touch_start_wait: 9;
uint32_t min_time_ck8m_off: 8;
};
uint32_t val;
}
union {
struct {
uint32_t wifi_wait_timer: 9;
uint32_t wifi_powerup_timer: 7;
uint32_t rom_ram_wait_timer: 9;
uint32_t rom_ram_powerup_timer: 7;
};
uint32_t val;
}
union {
struct {
uint32_t rtc_wait_timer: 9;
uint32_t rtc_powerup_timer: 7;
uint32_t dg_wrap_wait_timer: 9;
uint32_t dg_wrap_powerup_timer: 7;
};
uint32_t val;
}
union {
struct {
uint32_t sw_stall_appcpu_c0: 2;
uint32_t sw_stall_procpu_c0: 2;
uint32_t sw_appcpu_rst: 1;
uint32_t sw_procpu_rst: 1;
uint32_t bb_i2c_force_pd: 1;
uint32_t bb_i2c_force_pu: 1;
uint32_t bbpll_i2c_force_pd: 1;
uint32_t bbpll_i2c_force_pu: 1;
uint32_t bbpll_force_pd: 1;
uint32_t bbpll_force_pu: 1;
uint32_t xtl_force_pd: 1;
uint32_t xtl_force_pu: 1;
uint32_t bias_sleep_folw_8m: 1;
uint32_t bias_force_sleep: 1;
uint32_t bias_force_nosleep: 1;
uint32_t bias_i2c_folw_8m: 1;
uint32_t bias_i2c_force_pd: 1;
uint32_t bias_i2c_force_pu: 1;
uint32_t bias_core_folw_8m: 1;
uint32_t bias_core_force_pd: 1;
uint32_t bias_core_force_pu: 1;
uint32_t xtl_force_iso: 1;
uint32_t pll_force_iso: 1;
uint32_t analog_force_iso: 1;
uint32_t xtl_force_noiso: 1;
uint32_t pll_force_noiso: 1;
uint32_t analog_force_noiso: 1;
uint32_t dg_wrap_force_rst: 1;
uint32_t dg_wrap_force_norst: 1;
uint32_t sw_sys_rst: 1;
};
uint32_t val;
}
uint32_t
union {
struct {
uint32_t slp_val_hi: 16;
uint32_t main_timer_alarm_en: 1;
uint32_t reserved17: 15;
};
uint32_t val;
}
uint32_t
union {
struct {
uint32_t reserved0: 20;
uint32_t touch_wakeup_force_en: 1;
uint32_t ulp_cp_wakeup_force_en: 1;
uint32_t apb2rtc_bridge_sel: 1;
uint32_t touch_slp_timer_en: 1;
uint32_t ulp_cp_slp_timer_en: 1;
uint32_t reserved25: 3;
uint32_t sdio_active_ind: 1;
uint32_t slp_wakeup: 1;
uint32_t slp_reject: 1;
uint32_t sleep_en: 1;
};
uint32_t val;
}
union {
struct {
uint32_t ulp_cp_subtimer_prediv: 8;
uint32_t min_slp_val: 8;
uint32_t rtcmem_wait_timer: 9;
uint32_t rtcmem_powerup_timer: 7;
};
uint32_t val;
}
union {
struct {
uint32_t reserved0: 23;
uint32_t plla_force_pd: 1;
uint32_t plla_force_pu: 1;
uint32_t bbpll_cal_slp_start: 1;
uint32_t pvtmon_pu: 1;
uint32_t txrf_i2c_pu: 1;
uint32_t rfrx_pbus_pu: 1;
uint32_t reserved29: 1;
uint32_t ckgen_i2c_pu: 1;
uint32_t pll_i2c_pu: 1;
};
uint32_t val;
}
union {
struct {
uint32_t reset_cause_procpu: 6;
uint32_t reset_cause_appcpu: 6;
uint32_t appcpu_stat_vector_sel: 1;
uint32_t procpu_stat_vector_sel: 1;
uint32_t reserved14: 18;
};
uint32_t val;
}
union {
struct {
uint32_t wakeup_cause: 11;
uint32_t rtc_wakeup_ena: 11;
uint32_t gpio_wakeup_filter: 1;
uint32_t reserved23: 9;
};
uint32_t val;
}
union {
struct {
uint32_t slp_wakeup: 1;
uint32_t slp_reject: 1;
uint32_t sdio_idle: 1;
uint32_t rtc_wdt: 1;
uint32_t rtc_time_valid: 1;
uint32_t rtc_ulp_cp: 1;
uint32_t rtc_touch: 1;
uint32_t rtc_brown_out: 1;
uint32_t rtc_main_timer: 1;
uint32_t reserved9: 23;
};
uint32_t val;
}
union {
struct {
uint32_t slp_wakeup: 1;
uint32_t slp_reject: 1;
uint32_t sdio_idle: 1;
uint32_t rtc_wdt: 1;
uint32_t rtc_time_valid: 1;
uint32_t rtc_ulp_cp: 1;
uint32_t rtc_touch: 1;
uint32_t rtc_brown_out: 1;
uint32_t rtc_main_timer: 1;
uint32_t reserved9: 23;
};
uint32_t val;
}
union {
struct {
uint32_t slp_wakeup: 1;
uint32_t slp_reject: 1;
uint32_t sdio_idle: 1;
uint32_t rtc_wdt: 1;
uint32_t rtc_time_valid: 1;
uint32_t rtc_sar: 1;
uint32_t rtc_touch: 1;
uint32_t rtc_brown_out: 1;
uint32_t rtc_main_timer: 1;
uint32_t reserved9: 23;
};
uint32_t val;
}
union {
struct {
uint32_t slp_wakeup: 1;
uint32_t slp_reject: 1;
uint32_t sdio_idle: 1;
uint32_t rtc_wdt: 1;
uint32_t rtc_time_valid: 1;
uint32_t rtc_sar: 1;
uint32_t rtc_touch: 1;
uint32_t rtc_brown_out: 1;
uint32_t rtc_main_timer: 1;
uint32_t reserved9: 23;
};
uint32_t val;
}
uint32_t
uint32_t
uint32_t
uint32_t
union {
struct {
uint32_t reserved0: 4;
uint32_t ck8m_div: 2;
uint32_t enb_ck8m: 1;
uint32_t enb_ck8m_div: 1;
uint32_t dig_xtal32k_en: 1;
uint32_t dig_clk8m_d256_en: 1;
uint32_t dig_clk8m_en: 1;
uint32_t ck8m_dfreq_force: 1;
uint32_t ck8m_div_sel: 3;
uint32_t xtal_force_nogating: 1;
uint32_t ck8m_force_nogating: 1;
uint32_t ck8m_dfreq: 8;
uint32_t ck8m_force_pd: 1;
uint32_t ck8m_force_pu: 1;
uint32_t soc_clk_sel: 2;
uint32_t fast_clk_rtc_sel: 1;
uint32_t ana_clk_rtc_sel: 2;
};
uint32_t val;
}
union {
struct {
uint32_t reserved0: 21;
uint32_t sdio_pd_en: 1;
uint32_t sdio_force: 1;
uint32_t sdio_tieh: 1;
uint32_t reg1p8_ready: 1;
uint32_t drefl_sdio: 2;
uint32_t drefm_sdio: 2;
uint32_t drefh_sdio: 2;
uint32_t xpd_sdio: 1;
};
uint32_t val;
}
union {
struct {
uint32_t reserved0: 30;
uint32_t wakeup0_lv: 1;
uint32_t wakeup1_lv: 1;
};
uint32_t val;
}
union {
struct {
uint32_t reserved0: 24;
uint32_t gpio_reject_en: 1;
uint32_t sdio_reject_en: 1;
uint32_t light_slp_reject_en: 1;
uint32_t deep_slp_reject_en: 1;
uint32_t reject_cause: 4;
};
uint32_t val;
}
union {
struct {
uint32_t reserved0: 29;
uint32_t cpusel_conf: 1;
uint32_t cpuperiod_sel: 2;
};
uint32_t val;
}
union {
struct {
uint32_t reserved0: 3;
uint32_t lslp_mem_force_pd: 1;
uint32_t lslp_mem_force_pu: 1;
uint32_t rom0_force_pd: 1;
uint32_t rom0_force_pu: 1;
uint32_t inter_ram0_force_pd: 1;
uint32_t inter_ram0_force_pu: 1;
uint32_t inter_ram1_force_pd: 1;
uint32_t inter_ram1_force_pu: 1;
uint32_t inter_ram2_force_pd: 1;
uint32_t inter_ram2_force_pu: 1;
uint32_t inter_ram3_force_pd: 1;
uint32_t inter_ram3_force_pu: 1;
uint32_t inter_ram4_force_pd: 1;
uint32_t inter_ram4_force_pu: 1;
uint32_t wifi_force_pd: 1;
uint32_t wifi_force_pu: 1;
uint32_t dg_wrap_force_pd: 1;
uint32_t dg_wrap_force_pu: 1;
uint32_t reserved21: 3;
uint32_t rom0_pd_en: 1;
uint32_t inter_ram0_pd_en: 1;
uint32_t inter_ram1_pd_en: 1;
uint32_t inter_ram2_pd_en: 1;
uint32_t inter_ram3_pd_en: 1;
uint32_t inter_ram4_pd_en: 1;
uint32_t wifi_pd_en: 1;
uint32_t dg_wrap_pd_en: 1;
};
uint32_t val;
}
union {
struct {
uint32_t reserved0: 24;
uint32_t dbg_atten: 2;
uint32_t enb_sck_xtal: 1;
uint32_t inc_heartbeat_refresh: 1;
uint32_t dec_heartbeat_period: 1;
uint32_t inc_heartbeat_period: 1;
uint32_t dec_heartbeat_width: 1;
uint32_t rst_bias_i2c: 1;
};
uint32_t val;
}
union {
struct {
uint32_t reserved0: 7;
uint32_t sck_dcap_force: 1;
uint32_t dig_dbias_slp: 3;
uint32_t dig_dbias_wak: 3;
uint32_t sck_dcap: 8;
uint32_t rtc_dbias_slp: 3;
uint32_t rtc_dbias_wak: 3;
uint32_t rtc_dboost_force_pd: 1;
uint32_t rtc_dboost_force_pu: 1;
uint32_t rtc_force_pd: 1;
uint32_t rtc_force_pu: 1;
};
uint32_t val;
}
union {
struct {
uint32_t fastmem_force_noiso: 1;
uint32_t fastmem_force_iso: 1;
uint32_t slowmem_force_noiso: 1;
uint32_t slowmem_force_iso: 1;
uint32_t rtc_force_iso: 1;
uint32_t force_noiso: 1;
uint32_t fastmem_folw_cpu: 1;
uint32_t fastmem_force_lpd: 1;
uint32_t fastmem_force_lpu: 1;
uint32_t slowmem_folw_cpu: 1;
uint32_t slowmem_force_lpd: 1;
uint32_t slowmem_force_lpu: 1;
uint32_t fastmem_force_pd: 1;
uint32_t fastmem_force_pu: 1;
uint32_t fastmem_pd_en: 1;
uint32_t slowmem_force_pd: 1;
uint32_t slowmem_force_pu: 1;
uint32_t slowmem_pd_en: 1;
uint32_t pwc_force_pd: 1;
uint32_t pwc_force_pu: 1;
uint32_t pd_en: 1;
uint32_t reserved21: 11;
};
uint32_t val;
}
union {
struct {
uint32_t reserved0: 7;
uint32_t dig_iso_force_off: 1;
uint32_t dig_iso_force_on: 1;
uint32_t dg_pad_autohold: 1;
uint32_t clr_dg_pad_autohold: 1;
uint32_t dg_pad_autohold_en: 1;
uint32_t dg_pad_force_noiso: 1;
uint32_t dg_pad_force_iso: 1;
uint32_t dg_pad_force_unhold: 1;
uint32_t dg_pad_force_hold: 1;
uint32_t rom0_force_iso: 1;
uint32_t rom0_force_noiso: 1;
uint32_t inter_ram0_force_iso: 1;
uint32_t inter_ram0_force_noiso: 1;
uint32_t inter_ram1_force_iso: 1;
uint32_t inter_ram1_force_noiso: 1;
uint32_t inter_ram2_force_iso: 1;
uint32_t inter_ram2_force_noiso: 1;
uint32_t inter_ram3_force_iso: 1;
uint32_t inter_ram3_force_noiso: 1;
uint32_t inter_ram4_force_iso: 1;
uint32_t inter_ram4_force_noiso: 1;
uint32_t wifi_force_iso: 1;
uint32_t wifi_force_noiso: 1;
uint32_t dg_wrap_force_iso: 1;
uint32_t dg_wrap_force_noiso: 1;
};
uint32_t val;
}
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
union {
struct {
uint32_t reserved0: 7;
uint32_t pause_in_slp: 1;
uint32_t appcpu_reset_en: 1;
uint32_t procpu_reset_en: 1;
uint32_t flashboot_mod_en: 1;
uint32_t sys_reset_length: 3;
uint32_t cpu_reset_length: 3;
uint32_t level_int_en: 1;
uint32_t edge_int_en: 1;
uint32_t stg3: 3;
uint32_t stg2: 3;
uint32_t stg1: 3;
uint32_t stg0: 3;
uint32_t en: 1;
};
uint32_t val;
}
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
uint32_t
union {
struct {
uint32_t adc1_hold_force: 1;
uint32_t adc2_hold_force: 1;
uint32_t pdac1_hold_force: 1;
uint32_t pdac2_hold_force: 1;
uint32_t sense1_hold_force: 1;
uint32_t sense2_hold_force: 1;
uint32_t sense3_hold_force: 1;
uint32_t sense4_hold_force: 1;
uint32_t touch_pad0_hold_force: 1;
uint32_t touch_pad1_hold_force: 1;
uint32_t touch_pad2_hold_force: 1;
uint32_t touch_pad3_hold_force: 1;
uint32_t touch_pad4_hold_force: 1;
uint32_t touch_pad5_hold_force: 1;
uint32_t touch_pad6_hold_force: 1;
uint32_t touch_pad7_hold_force: 1;
uint32_t x32p_hold_force: 1;
uint32_t x32n_hold_force: 1;
uint32_t reserved18: 14;
};
uint32_t val;
}
union {
struct {
uint32_t ext_wakeup1_sel: 18;
uint32_t ext_wakeup1_status_clr: 1;
uint32_t reserved19: 13;
};
uint32_t val;
}
Related Functions
Found 19 other functions taking a rtc_cntl_dev_s
argument:
Function
Description
Disable a particular stage of the RWDT
Feed the RWDT Resets the current timer count and current stage.
Clear the RWDT interrupt status.
Disable the RWDT
Enable write protection of the RWDT registers
Disable write protection of the RWDT registers
Enable the RWDT interrupt.
Enable the RWDT
Check if the RWDT is enabled
Configure a particular stage of the RWDT
Enable or disable RWDT edge interrupt
Enable or disable RWDT level interrupt
Set the length of the CPU reset action
Set the length of the system reset action
Enable/Disable the RWDT flashboot mode.
Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU
Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU
Enable/Disable the RWDT pause during sleep functionality
Check if the RWDT interrupt has been triggered
References
Code
Location
Scope
Referrer
Instances
Instance
Scope
Location
Project