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SourceVuESP-IDF Framework and ExamplesESP-IDFi2s_pdm_tx_clk_config_t

i2s_pdm_tx_clk_config_t struct

I2S clock configuration for PDM TX mode

Syntax

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Summary

Declaration

from i2s_pdm.h:343

typedef struct { uint32_t sample_rate_hz; i2s_clock_src_t clk_src; i2s_mclk_multiple_t mclk_multiple; uint32_t up_sample_fp; uint32_t up_sample_fs; uint32_t bclk_div; } i2s_pdm_tx_clk_config_t;

Fields

Field

Declared as

Description

i2s_pdm_tx_clk_config_t::sample_rate_hz

uint32_t

I2S sample rate, not suggest to exceed 48000 Hz, otherwise more glitches and noise may appear.

i2s_pdm_tx_clk_config_t::clk_src

i2s_clock_src_t

Choose clock source.

i2s_pdm_tx_clk_config_t::mclk_multiple

i2s_mclk_multiple_t

The multiple of MCLK to the sample rate.

i2s_pdm_tx_clk_config_t::up_sample_fp

uint32_t

Up-sampling param fp.

i2s_pdm_tx_clk_config_t::up_sample_fs

uint32_t

Up-sampling param fs, not allowed to be greater than 480.

i2s_pdm_tx_clk_config_t::bclk_div

uint32_t

The division from MCLK to BCLK. The minimum value is I2S_PDM_TX_BCLK_DIV_MIN. It will be set to I2S_PDM_TX_BCLK_DIV_MIN by default if it is smaller than I2S_PDM_TX_BCLK_DIV_MIN.

References

Code

Location

Scope

Referrer

typedef struct {

} i2s_pdm_tx_clk_config_t;

static esp_err_t i2s_pdm_tx_calculate_clock(i2s_chan_handle_t handle, const i2s_pdm_tx_clk_config_t *clk_cfg, i2s_hal_clock_info_t *clk_info)

i2s_pdm_tx_calculate_clock()

i2s_pdm_tx_calculate_clock()::clk_cfg

i2s_pdm_tx_clk_config_t *pdm_tx_clk = (i2s_pdm_tx_clk_config_t *)clk_cfg;

i2s_pdm_tx_calculate_clock()

static esp_err_t i2s_pdm_tx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_tx_clk_config_t *clk_cfg)

i2s_pdm_tx_set_clock()

i2s_pdm_tx_set_clock()::clk_cfg

memcpy(&(pdm_tx_cfg->clk_cfg), clk_cfg, sizeof(i2s_pdm_tx_clk_config_t));

i2s_pdm_tx_set_clock()

esp_err_t i2s_channel_reconfig_pdm_tx_clock(i2s_chan_handle_t handle, const i2s_pdm_tx_clk_config_t *clk_cfg)

i2s_channel_reconfig_pdm_tx_clock()

i2s_channel_reconfig_pdm_tx_clock()::clk_cfg

} i2s_pdm_tx_clk_config_t;

i2s_pdm_tx_clk_config_t

i2s_pdm_tx_clk_config_t clk_cfg; /*!< PDM TX clock configurations, can be generated by macro I2S_PDM_TX_CLK_DEFAULT_CONFIG */

i2s_pdm_tx_config_t

i2s_pdm_tx_config_t::clk_cfg

esp_err_t i2s_channel_reconfig_pdm_tx_clock(i2s_chan_handle_t handle, const i2s_pdm_tx_clk_config_t *clk_cfg);

i2s_channel_reconfig_pdm_tx_clock()

i2s_channel_reconfig_pdm_tx_clock()::clk_cfg

Call Tree

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Data Use

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Implementations

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Instances

Instance

Scope

Location

Project

i2s_pdm_tx_config_t::clk_cfg

i2s_pdm_tx_config_t

i2s_channel_reconfig_pdm_tx_clock()::clk_cfg

i2s_channel_reconfig_pdm_tx_clock()

i2s_pdm_tx_calculate_clock()::clk_cfg

i2s_pdm_tx_calculate_clock()

i2s_pdm_tx_set_clock()::clk_cfg

i2s_pdm_tx_set_clock()

i2s_channel_reconfig_pdm_tx_clock()::clk_cfg

i2s_channel_reconfig_pdm_tx_clock()

Lifecycle

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