i2c_ll_write_txfifo() function

Beginning address of the peripheral registers

Pointer to data buffer

Amount of data needs to be written

Clear I2C interrupt status

Update I2C configuration

Write I2C hardware command register

Disable I2C interrupt

Configure I2C hardware filter

Read the I2C hardware rxFIFO

Reset I2C txFIFO

Get I2C interrupt status

Configure I2C timeout

Set I2C source clock

Get I2C txFIFO writable length

Reset I2C rxFIFO

Enable I2C interrupt

Configure I2C stop timing

Check if the I2C bus is busy

Get the rxFIFO readable length

Disable I2C slave TX interrupt

Configure I2C slave address

Get I2C interrupt status register address

Clear I2C clock stretch status

Enable I2C slave RX interrupt

Set fractional divider

Set I2C txFIFO empty threshold

Set I2C rxFIFO full threshold

Set the I2C data mode, LSB or MSB

Get I2C hardware filter configuration

Enable I2C peripheral controller clock

Get I2C timeout configuration

Start I2C transfer

Get I2C start timing configuration

Get I2C stop timing configuration

Enable I2C slave to automatically send data when addressed by the master

Get I2C master interrupt event

Configure I2C stop timing

Get I2C sda timing configuration

Configure I2C memory access mode, FIFO mode or non-FIFO mode

Configure I2C start timing

Reset I2C master FSM. When the master FSM is stuck, call this function to reset the FSM

Init I2C master

Get status of i2c slave

Get I2C SCL timing configuration

Configure I2C SCL timing

Enable I2C master TX interrupt

Enable I2C master RX interrupt

Disable I2C master TX interrupt

Init I2C slave

Enable I2C slave clock stretch.

Set I2C clock stretch protect num

Get I2C slave interrupt event

Disable I2C master RX interrupt

Configure I2C SCL timing

Get the I2C data mode

Get I2C SCL timing configuration

Configure the I2C bus timing related register.

Get clock configurations from registers

Get clock configurations from registers

Set fractional divider

Clear I2C bus, when the slave is stuck in a deadlock and keeps pulling the bus low, master can controls the SCL bus to generate 9 CLKs. Note: The master cannot detect if deadlock happens, but when the scl_st_to interrupt is generated, a deadlock may occur.

Get the clear bus state

Disable I2C slave RX interrupt

Check if i2c command is done.

Get the I2C hardware version

Enable the I2C slave to respond to broadcast address