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SourceVuESP-IDF Framework and ExamplesESP-IDFcache_bus_mask_t

cache_bus_mask_t enum

Syntax

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Summary

Declaration

from cache_types.h:28

enum { CACHE_BUS_IBUS0 = BIT(0), CACHE_BUS_IBUS1 = BIT(1), CACHE_BUS_IBUS2 = BIT(2), CACHE_BUS_DBUS0 = BIT(3), CACHE_BUS_DBUS1 = BIT(4), CACHE_BUS_DBUS2 = BIT(5), };

Values

Value

Declared as

cache_bus_mask_t::CACHE_BUS_IBUS0

= BIT

cache_bus_mask_t::CACHE_BUS_IBUS1

= BIT

cache_bus_mask_t::CACHE_BUS_IBUS2

= BIT

cache_bus_mask_t::CACHE_BUS_DBUS0

= BIT

cache_bus_mask_t::CACHE_BUS_DBUS1

= BIT

cache_bus_mask_t::CACHE_BUS_DBUS2

= BIT

References

Code

Location

Scope

Referrer

typedef enum {

cache_types.h:28

} cache_bus_mask_t;

cache_types.h:35

cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, drom_load_addr_aligned, drom_size);

bootloader_utility.c:931

set_cache_and_start_app()

static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)

cache_ll_l1_get_bus()

cache_bus_mask_t mask = (cache_bus_mask_t)0;

cache_ll_l1_get_bus()

mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS2);

cache_ll_l1_get_bus()

mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS1);

cache_ll_l1_get_bus()

mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0));

cache_ll_l1_get_bus()

mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS0);

cache_ll_l1_get_bus()

mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));

cache_ll_l1_get_bus()

mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0));

cache_ll_l1_get_bus()

mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS1);

cache_ll_l1_get_bus()

mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS0);

cache_ll_l1_get_bus()

static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)

cache_ll_l1_enable_bus()

cache_ll_l1_enable_bus()::mask

static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)

cache_ll_l1_get_enabled_bus()

cache_bus_mask_t mask = (cache_bus_mask_t)0;

cache_ll_l1_get_enabled_bus()

mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0));

cache_ll_l1_get_enabled_bus()

mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0));

cache_ll_l1_get_enabled_bus()

mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0));

cache_ll_l1_get_enabled_bus()

mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0));

cache_ll_l1_get_enabled_bus()

mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0));

cache_ll_l1_get_enabled_bus()

mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0));

cache_ll_l1_get_enabled_bus()

mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0));

cache_ll_l1_get_enabled_bus()

mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0));

cache_ll_l1_get_enabled_bus()

mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0));

cache_ll_l1_get_enabled_bus()

mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0));

cache_ll_l1_get_enabled_bus()

static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)

cache_ll_l1_disable_bus()

cache_ll_l1_disable_bus()::mask

} cache_bus_mask_t;

cache_types.h:35

cache_bus_mask_t

cache_bus_mask_t cache_bus_mask_core0 = cache_ll_l1_get_enabled_bus(0);

cpu_start.c:363

do_multicore_settings()

cache_bus_mask_t bus_id; //cache bus mask of this region

esp_mmu_map.c:87

mem_region_::bus_id

static cache_bus_mask_t s_get_bus_mask(uint32_t vaddr_start, uint32_t len)

esp_mmu_map.c:120

s_get_bus_mask()

cache_bus_mask_t bus_mask = s_get_bus_mask((uint32_t)&_instruction_reserved_start, irom_len_to_reserve);

esp_mmu_map.c:144

s_reserve_irom_region()

cache_bus_mask_t bus_mask = s_get_bus_mask((uint32_t)&_rodata_reserved_start, drom_len_to_reserve);

esp_mmu_map.c:172

s_reserve_drom_region()

cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, vaddr_start, size);

esp_mmu_map.c:428

cache_bus_mask_t bus_id; //bus_id mask, for accessible cache buses

ext_mem_layout.h:23

mmu_mem_region_t

mmu_mem_region_t::bus_id

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return

cache_ll_l1_get_bus()

cache_ll_l1_enable_bus()::mask

cache_ll_l1_enable_bus()

return

cache_ll_l1_get_enabled_bus()

cache_ll_l1_disable_bus()::mask

cache_ll_l1_disable_bus()

mem_region_::bus_id

esp_mmu_map.c:87

return

s_get_bus_mask()

esp_mmu_map.c:120

mmu_mem_region_t::bus_id

mmu_mem_region_t

ext_mem_layout.h:23

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