ESP-IDF
DPORT_SET_PERI_REG_MASK
is only used within ESP-IDF.
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ESP-IDF Framework and Examples
ESP-IDF
DPORT_SET_PERI_REG_MASK
DPORT_SET_PERI_REG_MASK macro
Syntax
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Summary
Declaration
from
dport_access.h:184
#define
DPORT_SET_PERI_REG_MASK
(
reg
,
mask
)
DPORT_WRITE_PERI_REG
(
(
reg
)
,
(
DPORT_READ_PERI_REG
(
reg
)
|
(
mask
)
)
)
Arguments
Argument
reg
mask
Examples
References
from
examples
Code
Location
#define
DPORT_SET_PERI_REG_MASK
(
reg
,
mask
)
DPORT_WRITE_PERI_REG
(
(
reg
)
,
(
DPORT_READ_PERI_REG
(
reg
)
|
(
mask
)
)
)
dport_access.h:184
DPORT_SET_PERI_REG_MASK
(
DPORT_PERI_CLK_EN_REG
,
DPORT_PERI_EN_AES
)
;
aes_ll.h:38
DPORT_SET_PERI_REG_MASK
(
DPORT_PERI_RST_EN_REG
,
DPORT_PERI_EN_AES
)
;
aes_ll.h:53
DPORT_SET_PERI_REG_MASK
(
DPORT_CACHE_IA_INT_EN_REG
,
cache_err_int.c:51
DPORT_SET_PERI_REG_MASK
(
DPORT_CACHE_IA_INT_EN_REG
,
cache_err_int.c:59
DPORT_SET_PERI_REG_MASK
(
I2S_CLKM_CONF_REG
(
0
)
,
I2S_CLKA_ENA
)
;
clk.c:289
DPORT_SET_PERI_REG_MASK
(
I2S_CLKM_CONF_REG
(
1
)
,
I2S_CLKA_ENA
)
;
clk.c:290
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_RST_EN_REG
,
common_perip_clk
)
;
clk.c:294
DPORT_SET_PERI_REG_MASK
(
DPORT_PERI_RST_EN_REG
,
hwcrypto_perip_clk
)
;
clk.c:298
DPORT_SET_PERI_REG_MASK
(
periph_ll_get_clk_en_reg
(
periph
)
,
periph_ll_get_clk_en_mask
(
periph
)
)
;
clk_gate_ll.h:225
DPORT_SET_PERI_REG_MASK
(
periph_ll_get_rst_en_reg
(
periph
)
,
periph_ll_get_rst_en_mask
(
periph
,
false
)
)
;
clk_gate_ll.h:232
DPORT_SET_PERI_REG_MASK
(
DPORT_WIFI_CLK_EN_REG
,
DPORT_WIFI_CLK_WIFI_BT_COMMON_M
)
;
clk_gate_ll.h:237
DPORT_SET_PERI_REG_MASK
(
periph_ll_get_rst_en_reg
(
periph
)
,
periph_ll_get_rst_en_mask
(
periph
,
false
)
)
;
clk_gate_ll.h:247
DPORT_SET_PERI_REG_MASK
(
DPORT_WIFI_CLK_EN_REG
,
DPORT_WIFI_CLK_WIFI_EN_M
)
;
clk_gate_ll.h:259
DPORT_SET_PERI_REG_MASK
(
DPORT_CORE_RST_EN_REG
,
0
)
;
clk_gate_ll.h:266
DPORT_SET_PERI_REG_MASK
(
DPORT_APPCPU_CTRL_B_REG
,
DPORT_APPCPU_CLKGATE_EN
)
;
cpu_start.c:299
DPORT_SET_PERI_REG_MASK
(
DPORT_APPCPU_CTRL_A_REG
,
DPORT_APPCPU_RESETTING
)
;
cpu_start.c:301
DPORT_SET_PERI_REG_MASK
(
DPORT_HOST_INF_SEL_REG
,
1
<
<
14
)
;
esp_psram_impl_quad.c:314
DPORT_SET_PERI_REG_MASK
(
DPORT_PRO_CACHE_CTRL_REG
,
DPORT_PRO_DRAM_HL
)
;
esp_psram_impl_quad.c:1133
DPORT_SET_PERI_REG_MASK
(
DPORT_APP_CACHE_CTRL_REG
,
DPORT_APP_DRAM_HL
)
;
esp_psram_impl_quad.c:1134
DPORT_SET_PERI_REG_MASK
(
DPORT_PRO_CACHE_CTRL_REG
,
DPORT_PRO_DRAM_SPLIT
)
;
esp_psram_impl_quad.c:1136
DPORT_SET_PERI_REG_MASK
(
DPORT_APP_CACHE_CTRL_REG
,
DPORT_APP_DRAM_SPLIT
)
;
esp_psram_impl_quad.c:1137
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_CLK_EN_REG
,
DPORT_I2S0_CLK_EN
)
;
i2s_ll.h:97
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_CLK_EN_REG
,
DPORT_I2S1_CLK_EN
)
;
i2s_ll.h:99
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_RST_EN_REG
,
DPORT_I2S0_RST
)
;
i2s_ll.h:123
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_RST_EN_REG
,
DPORT_I2S1_RST
)
;
i2s_ll.h:126
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_CLK_EN_REG
,
DPORT_LEDC_CLK_EN
)
;
ledc_ll.h:52
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_RST_EN_REG
,
DPORT_LEDC_RST
)
;
ledc_ll.h:68
DPORT_SET_PERI_REG_MASK
(
DPORT_PERI_CLK_EN_REG
,
DPORT_PERI_EN_RSA
)
;
mpi_ll.h:30
DPORT_SET_PERI_REG_MASK
(
DPORT_PERI_RST_EN_REG
,
DPORT_PERI_EN_RSA
)
;
mpi_ll.h:45
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_CLK_EN_REG
,
DPORT_PCNT_CLK_EN
)
;
pcnt_ll.h:452
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_RST_EN_REG
,
DPORT_PCNT_RST
)
;
pcnt_ll.h:468
DPORT_SET_PERI_REG_MASK
(
DPORT_CORE_RST_EN_REG
,
MODEM_RESET_FIELD_WHEN_PU
)
;
phy_init.c:404
DPORT_SET_PERI_REG_MASK
(
DPORT_WIFI_CLK_EN_REG
,
DPORT_WIFI_CLK_SDIO_HOST_EN
)
;
sdmmc_ll.h:105
DPORT_SET_PERI_REG_MASK
(
DPORT_CORE_RST_EN_REG
,
DPORT_SDIO_HOST_RST
)
;
sdmmc_ll.h:122
DPORT_SET_PERI_REG_MASK
(
DPORT_PERI_CLK_EN_REG
,
DPORT_PERI_EN_SHA
)
;
sha_ll.h:29
DPORT_SET_PERI_REG_MASK
(
DPORT_PERI_RST_EN_REG
,
DPORT_PERI_EN_SHA
)
;
sha_ll.h:44
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_CLK_EN_REG
,
DPORT_SPI01_CLK_EN
)
;
spi_ll.h:71
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_CLK_EN_REG
,
DPORT_SPI2_CLK_EN
)
;
spi_ll.h:74
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_CLK_EN_REG
,
DPORT_SPI3_CLK_EN
)
;
spi_ll.h:77
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_RST_EN_REG
,
DPORT_SPI01_RST
)
;
spi_ll.h:111
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_RST_EN_REG
,
DPORT_SPI2_RST
)
;
spi_ll.h:115
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_RST_EN_REG
,
DPORT_SPI3_RST
)
;
spi_ll.h:119
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_CLK_EN_REG
,
DPORT_SPI_DMA_CLK_EN
)
;
spi_ll.h:1086
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_RST_EN_REG
,
DPORT_SPI_DMA_RST
)
;
spi_ll.h:1104
DPORT_SET_PERI_REG_MASK
(
DPORT_CORE_RST_EN_REG
,
system_internal.c:41
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_RST_EN_REG
,
system_internal.c:48
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_RST_EN_REG
,
DPORT_UART_RST
)
;
uart_ll.h:115
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_RST_EN_REG
,
DPORT_UART1_RST
)
;
uart_ll.h:119
DPORT_SET_PERI_REG_MASK
(
DPORT_PERIP_RST_EN_REG
,
DPORT_UART2_RST
)
;
uart_ll.h:123
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