adiv5_ap struct

Queue an AP register read.

Queue an AP register write.

Asynchronous (queued) read of a word from memory or a system register.

Asynchronous (queued) write of a word to memory or a system register.

Synchronous read of a word from memory or a system register. As a side effect, this flushes any queued transactions.

Synchronous write of a word to memory or a system register. As a side effect, this flushes any queued transactions.

Initialize a DAP. This sets up the power domains, prepares the DP for further use, and arranges to use AP #0 for all AP operations until dap_ap-select() changes that policy.

Select the AP register bank

Select the AP register bank

Queue transactions setting up transfer parameters for the currently selected MEM-AP. Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2 initiate data reads or writes using memory or peripheral addresses. If the CSW is configured for it, the TAR may be automatically incremented after each transfer.

Queue transactions setting up transfer parameters for the currently selected MEM-AP. If transfer size or packing has not been probed, run the queue, read back CSW and check if the requested transfer mode is supported.

Wrapper around struct rtp_ops::ap_header.

Wrapper around struct rtp_ops::mem_ap_header. Input parameter @a retval is propagated.

Queue transactions setting up transfer parameters for the currently selected MEM-AP. If transfer size or packing has not been probed, run the queue, read back CSW and check if the requested transfer mode is supported. If packing is not supported fallback and prepare CSW for unpacked transfer.

Synchronous write of a block of memory, using a specific access size.

Synchronous read of a block of memory, using a specific access size.

Helper to read CoreSight component's registers, either on the bus behind a MEM-AP or directly in the AP.

Read the CoreSight registers needed during ROM Table Parsing (RTP).

DP and MEM-AP register access through APACC and DPACC *