__DMA2D_HandleTypeDef::Instance field

DMA2D_MemToMemWithLCD

LCD_DSI_CmdMode_DoubleBuffering

DMA2D_RegToMemWithLCD

LCD_DSI

LCD_DSI_CmdMode_PartialRefresh

LCD_DSI_CmdMode_SingleBuffer

LCD_DSI_CmdMode_TearingEffect

LCD_DSI_CmdMode_TearingEffect_ExtPin

LCD_DSI_ULPM_Data

LCD_DSI_ULPM_DataClock

LCD_DSI_VideoMode_DoubleBuffering

LCD_DSI_VideoMode_SingleBuffer

Applications

Camera

Camera_To_USBDisk

Display

LCD_DSI_ImagesSlider

LCD_Paint

STM32F429I-Discovery

Demonstrations

STemWin

Applications

Display

LibJPEG

STemWin

Examples

DMA2D

STM32469I-Discovery

Applications

Display

LCD_DSI_ImagesSlider

LCD_Paint

Examples

DMA2D

LCD_DSI_CmdMode_DoubleBuffering

LCD_DSI

LCD_DSI_CmdMode_PartialRefresh

LCD_DSI_CmdMode_SingleBuffer

LCD_DSI_CmdMode_TearingEffect

LCD_DSI_CmdMode_TearingEffect_ExtPin

LCD_DSI_ULPM_Data

LCD_DSI_ULPM_DataClock

LCD_DSI_VideoMode_DoubleBuffering

LCD_DSI_VideoMode_SingleBuffer

STM324x9I_EVAL

Applications

Camera

Display

STemWin

Demonstrations

STemWin

MB1046

MB1063

Examples

DCMI

DCMI_CaptureMode

DCMI_SnapshotMode

DMA2D

DMA2D_MemoryToMemory

DMA2D_MemToMemWithLCD

stm32f4xx_hal_dma2d.h:130

DMA2D_RegToMemWithLCD

References

from 0/65 examples

Code

Location

Referrer

DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */

assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));

stm32f4xx_hal_dma2d.c:247

stm32f4xx_hal_dma2d.c:280

MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);

stm32f4xx_hal_dma2d.c:283

MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);

stm32f4xx_hal_dma2d.c:286

MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);

stm32f4xx_hal_dma2d.c:320

if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)

stm32f4xx_hal_dma2d.c:331

if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)

stm32f4xx_hal_dma2d.c:342

if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)

stm32f4xx_hal_dma2d.c:355

hdma2d->Instance->CR = 0U;

stm32f4xx_hal_dma2d.c:356

hdma2d->Instance->IFCR = 0x3FU;

stm32f4xx_hal_dma2d.c:357

hdma2d->Instance->FGOR = 0U;

stm32f4xx_hal_dma2d.c:358

hdma2d->Instance->BGOR = 0U;

stm32f4xx_hal_dma2d.c:359

hdma2d->Instance->FGPFCCR = 0U;

stm32f4xx_hal_dma2d.c:360

hdma2d->Instance->BGPFCCR = 0U;

stm32f4xx_hal_dma2d.c:361

hdma2d->Instance->OPFCCR = 0U;

stm32f4xx_hal_dma2d.c:685

__HAL_DMA2D_ENABLE(hdma2d);

HAL_DMA2D_Start()

__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);

stm32f4xx_hal_dma2d.c:721

HAL_DMA2D_Start_IT()

__HAL_DMA2D_ENABLE(hdma2d);

stm32f4xx_hal_dma2d.c:724

HAL_DMA2D_Start_IT()

WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);

stm32f4xx_hal_dma2d.c:755

HAL_DMA2D_BlendingStart()

__HAL_DMA2D_ENABLE(hdma2d);

stm32f4xx_hal_dma2d.c:761

HAL_DMA2D_BlendingStart()

WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);

stm32f4xx_hal_dma2d.c:792

HAL_DMA2D_BlendingStart_IT()

__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);

stm32f4xx_hal_dma2d.c:798

HAL_DMA2D_BlendingStart_IT()

__HAL_DMA2D_ENABLE(hdma2d);

stm32f4xx_hal_dma2d.c:801

HAL_DMA2D_BlendingStart_IT()

MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);

stm32f4xx_hal_dma2d.c:820

HAL_DMA2D_Abort()

while ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)

stm32f4xx_hal_dma2d.c:826

HAL_DMA2D_Abort()

__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);

stm32f4xx_hal_dma2d.c:844

HAL_DMA2D_Abort()

MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);

stm32f4xx_hal_dma2d.c:869

stm32f4xx_hal_dma2d.c:875

while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)

stm32f4xx_hal_dma2d.c:890

if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)

stm32f4xx_hal_dma2d.c:898

CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);

stm32f4xx_hal_dma2d.c:913

if ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))

HAL_DMA2D_Resume()

CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP | DMA2D_CR_START));

stm32f4xx_hal_dma2d.c:923

HAL_DMA2D_Resume()

SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);

stm32f4xx_hal_dma2d.c:952

HAL_DMA2D_EnableCLUT()

SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);

stm32f4xx_hal_dma2d.c:957

HAL_DMA2D_EnableCLUT()

WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);

stm32f4xx_hal_dma2d.c:991

stm32f4xx_hal_dma2d.c:994

MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),

stm32f4xx_hal_dma2d.c:998

SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);

stm32f4xx_hal_dma2d.c:1004

WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);

stm32f4xx_hal_dma2d.c:1007

MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),

stm32f4xx_hal_dma2d.c:1011

SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);

stm32f4xx_hal_dma2d.c:1046

WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);

stm32f4xx_hal_dma2d.c:1049

MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),

stm32f4xx_hal_dma2d.c:1053

__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);

stm32f4xx_hal_dma2d.c:1056

SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);

stm32f4xx_hal_dma2d.c:1062

WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);

stm32f4xx_hal_dma2d.c:1065

MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),

stm32f4xx_hal_dma2d.c:1069

__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);

stm32f4xx_hal_dma2d.c:1072

SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);

stm32f4xx_hal_dma2d.c:1109

WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);

stm32f4xx_hal_dma2d.c:1112

MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),

stm32f4xx_hal_dma2d.c:1116

SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);

stm32f4xx_hal_dma2d.c:1122

WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);

stm32f4xx_hal_dma2d.c:1125

MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),

stm32f4xx_hal_dma2d.c:1129

SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);

stm32f4xx_hal_dma2d.c:1166

WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);

stm32f4xx_hal_dma2d.c:1169

MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),

stm32f4xx_hal_dma2d.c:1173

__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);

stm32f4xx_hal_dma2d.c:1176

SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);

stm32f4xx_hal_dma2d.c:1182

WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);

stm32f4xx_hal_dma2d.c:1185

MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),

stm32f4xx_hal_dma2d.c:1189

__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);

stm32f4xx_hal_dma2d.c:1192

SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);

stm32f4xx_hal_dma2d.c:1210

const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */

stm32f4xx_hal_dma2d.c:1213

SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);

stm32f4xx_hal_dma2d.c:1218

reg = &(hdma2d->Instance->FGPFCCR);

stm32f4xx_hal_dma2d.c:1244

__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);

stm32f4xx_hal_dma2d.c:1268

const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */

stm32f4xx_hal_dma2d.c:1271

SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);

stm32f4xx_hal_dma2d.c:1276

reg = &(hdma2d->Instance->FGPFCCR);

stm32f4xx_hal_dma2d.c:1284

loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;

stm32f4xx_hal_dma2d.c:1300

loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;

stm32f4xx_hal_dma2d.c:1314

CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);

stm32f4xx_hal_dma2d.c:1335

if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)

stm32f4xx_hal_dma2d.c:1337

if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)

stm32f4xx_hal_dma2d.c:1347

if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)

stm32f4xx_hal_dma2d.c:1349

if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)

stm32f4xx_hal_dma2d.c:1358

CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);

stm32f4xx_hal_dma2d.c:1379

if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)

stm32f4xx_hal_dma2d.c:1384

while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)

stm32f4xx_hal_dma2d.c:1386

isrflags = READ_REG(hdma2d->Instance->ISR);

stm32f4xx_hal_dma2d.c:1398

__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);

stm32f4xx_hal_dma2d.c:1428

layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;

stm32f4xx_hal_dma2d.c:1429

layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;

stm32f4xx_hal_dma2d.c:1435

while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)

stm32f4xx_hal_dma2d.c:1437

isrflags = READ_REG(hdma2d->Instance->ISR);

stm32f4xx_hal_dma2d.c:1453

__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);

stm32f4xx_hal_dma2d.c:1484

__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC);

stm32f4xx_hal_dma2d.c:1502

uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);

stm32f4xx_hal_dma2d.c:1503

uint32_t crflags = READ_REG(hdma2d->Instance->CR);

stm32f4xx_hal_dma2d.c:1511

__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);

stm32f4xx_hal_dma2d.c:1517

__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);

stm32f4xx_hal_dma2d.c:1538

__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);

stm32f4xx_hal_dma2d.c:1541

__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);

stm32f4xx_hal_dma2d.c:1565

__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);

stm32f4xx_hal_dma2d.c:1568

__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);

stm32f4xx_hal_dma2d.c:1592

__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);

stm32f4xx_hal_dma2d.c:1595

__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);

stm32f4xx_hal_dma2d.c:1612

__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);

stm32f4xx_hal_dma2d.c:1615

__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);

stm32f4xx_hal_dma2d.c:1639

__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);

stm32f4xx_hal_dma2d.c:1642

__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);

stm32f4xx_hal_dma2d.c:1773

MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);

stm32f4xx_hal_dma2d.c:1776

WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);

stm32f4xx_hal_dma2d.c:1781

WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \

stm32f4xx_hal_dma2d.c:1791

MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);

stm32f4xx_hal_dma2d.c:1794

WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);

stm32f4xx_hal_dma2d.c:1799

WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \

stm32f4xx_hal_dma2d.c:1843

WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);

stm32f4xx_hal_dma2d.c:1846

MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),

stm32f4xx_hal_dma2d.c:1853

WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);

stm32f4xx_hal_dma2d.c:1856

MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),

stm32f4xx_hal_dma2d.c:1896

WRITE_REG(hdma2d->Instance->LWR, Line);

HAL_DMA2D_ProgramLineEvent()

__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);

stm32f4xx_hal_dma2d.c:1899

HAL_DMA2D_ProgramLineEvent()

SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);

stm32f4xx_hal_dma2d.c:1924

HAL_DMA2D_EnableDeadTime()

CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);

stm32f4xx_hal_dma2d.c:1947

HAL_DMA2D_DisableDeadTime()

MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));

stm32f4xx_hal_dma2d.c:1973

HAL_DMA2D_ConfigDeadTime()

MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL | DMA2D_NLR_PL), (Height | (Width << DMA2D_NLR_PL_Pos)));

stm32f4xx_hal_dma2d.c:2059

stm32f4xx_hal_dma2d.c:2062

WRITE_REG(hdma2d->Instance->OMAR, DstAddress);

stm32f4xx_hal_dma2d.c:2105

WRITE_REG(hdma2d->Instance->OCOLR, tmp);

stm32f4xx_hal_dma2d.c:2110

WRITE_REG(hdma2d->Instance->FGMAR, pdata);