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__HAL_RCC_TIM5_CLK_ENABLE
from the following samples and libraries:
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Examples
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HAL_TimeBase_TIM
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IWDG_Example
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IWDG_Example
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IWDG_Example
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IWDG_Example
STM32F446ZE-Nucleo
Examples
IWDG
IWDG_Example
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STM32 Libraries and Samples
HAL
__HAL_RCC_TIM5_CLK_ENABLE
__HAL_RCC_TIM5_CLK_ENABLE macro
Enable or disable the Low Speed APB (APB1) peripheral clock.
Syntax
Show:
Summary
Declaration
from
stm32f4xx_hal_rcc.h:468
#define
__HAL_RCC_TIM5_CLK_ENABLE
(
)
do
{
\
__IO
uint32_t
tmpreg
=
0x00U
;
\
SET_BIT
(
RCC
->
APB1ENR
,
RCC_APB1ENR_TIM5EN
)
;
\
\
tmpreg
=
READ_BIT
(
RCC
->
APB1ENR
,
RCC_APB1ENR_TIM5EN
)
;
\
UNUSED
(
tmpreg
)
;
\
}
while
(
0U
)
Notes
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Examples
__HAL_RCC_TIM5_CLK_ENABLE
is referenced by 20 libraries and example projects:
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