__HAL_RCC_PLLSAI_CONFIG macro
Macro to configure the PLLSAI clock multiplication and division factors.
Arguments
__PLLSAIM__
specifies the division factor for PLLSAI VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.
__PLLSAIN__
specifies the multiplication factor for PLLSAI VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432.
__PLLSAIP__
specifies division factor for OTG FS, SDIO and RNG clocks. This parameter must be a number in the range {2, 4, 6, or 8}.
__PLLSAIQ__
specifies the division factor for SAI clock This parameter must be a number between Min_Data = 2 and Max_Data = 15.
__PLLSAIR__
specifies the division factor for LTDC clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Notes
You have to set the PLLSAIM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 1 MHz to limit PLLI2S jitter. The PLLSAIM parameter is only used with STM32F446xx Devices You have to set the PLLSAIN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz. the PLLSAIP parameter is only available with STM32F446xx Devices the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices