LIS3DSH_STAT_ADDR macro

STAT Register: State Machine Register Read only register Default value: 0x00 7 LONG: LONG flag common to both State Machines 0 - no interrupt 1 - LongCounter interrupt flag 6 SYNCW: Common information for OUTW host action waiting 0 - no action waiting from Host 1 - Host action is waiting after OUTW command 5 SYNC1: 0 - State Machine 1 running normally 1 - SM1 stopped and waiting for restart request from SM2 4 SYNC2: 0 - State Machine 2 running normally 1 - SM2 stopped and waiting for restart request from SM1 3 INT_SM1: Interrupt signal on SM1 is reset when OUTS1 register is read 0 - no interrupt on State Machine 1 1 - State Machine 1 interrupt happened 2 INT_SM2: Interrupt signal on SM2 is reset when OUTS2 register is read 0 - no interrupt on State Machine 2 1 - State Machine 2 interrupt happened 1 DOR: Data OverRun bit 0 - no overrun 1 - data overrun 0 DRDY: New data are ready in output registers 0 - data not ready 1 - data ready