LIS3DSH_CTRL_REG3_ADDR macro

CTRL_REG3 Register: Control Register 3 Read Write register Default value: 0x00 7 DR_EN: Data-ready interrupt 0 - Data-ready interrupt disabled (Default) 1 - Data-ready interrupt enabled and routed to INT1 6 IEA: 0 - Interrupt signal active LOW (Default) 1 - Interrupt signal active HIGH 5 IEL: 0 - Interrupt latched (Default) 1 - Interrupt pulsed 4 INT2_EN: 0 - INT2 signal disabled (High-Z state) (Default) 1 - INT2 signal enabled (signal pin fully functional) 3 INT1_EN: 0 - INT1 (DRDY) signal disabled (High-Z state) (Default) 1 - INT1 (DRDY) signal enabled (signal pin fully functional) DR_EN bit in CTRL_REG3 register should be taken into account too 2 VLIFT: 0 - Vector filter disabled (Default) 1 - Vector filter enabled 1 Reserved 0 STRT: Soft Reset 0 - (Default) 1 - it resets the whole internal logic circuitry. It automatically returns to 0.