LIS302DL_FF_WU_SRC1_REG_ADDR macro

FF_WU_SRC_1 Register: Interrupt 1 source register. Reading at this address clears FF_WU_SRC_1 register and the FF, WU 1 interrupt and allow the refreshment of data in the FF_WU_SRC_1 register if the latched option was chosen. Read only register Default value: 0x00 7 Reserved 6 IA: Interrupt active. 0: no interrupt has been generated 1: one or more interrupts have been generated 5 ZH: Z high. 0: no interrupt 1: ZH event has occurred 4 ZL: Z low. 0: no interrupt 1: ZL event has occurred 3 YH: Y high. 0: no interrupt 1: YH event has occurred 2 YL: Y low. 0: no interrupt 1: YL event has occurred 1 YH: X high. 0: no interrupt 1: XH event has occurred 0 YL: X low. 0: no interrupt 1: XL event has occurred