__IM - syntax, references, description

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#define __IM volatile const /*! Defines 'read only' structure member permissions */

core_cm4.h:230

__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */

core_cm4.h:447

__IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */

core_cm4.h:461

__IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */

core_cm4.h:462

__IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */

core_cm4.h:463

__IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */

core_cm4.h:464

__IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */

core_cm4.h:465

__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */

core_cm4.h:727

__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */

core_cm4.h:769

__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */

core_cm4.h:833

__IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */

core_cm4.h:835

__IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */

core_cm4.h:836

__IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */

core_cm4.h:837

__IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */

core_cm4.h:838

__IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */

core_cm4.h:839

__IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */

core_cm4.h:840

__IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */

core_cm4.h:841

__IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */

core_cm4.h:842

__IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */

core_cm4.h:843

__IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */

core_cm4.h:844

__IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */

core_cm4.h:845

__IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */

core_cm4.h:846

__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */

core_cm4.h:913

__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */

core_cm4.h:1053

__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */

core_cm4.h:1060

__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */

core_cm4.h:1062

__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */

core_cm4.h:1064

__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */

core_cm4.h:1065

__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */

core_cm4.h:1066

__IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */

core_cm4.h:1068

__IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */

core_cm4.h:1069

__IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */

core_cm4.h:1075

__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */

core_cm4.h:1076

__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */

core_cm4.h:1215

__IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */

core_cm4.h:1315

__IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */

core_cm4.h:1316

__IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */

core_cm4.h:1317

__IM macro

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