gpio_irq_level enum

GPIO Interrupt level definitions (GPIO events) GPIO Interrupt levels An interrupt can be generated for every GPIO pin in 4 scenarios: * Level High: the GPIO pin is a logical 1 * Level Low: the GPIO pin is a logical 0 * Edge High: the GPIO has transitioned from a logical 0 to a logical 1 * Edge Low: the GPIO has transitioned from a logical 1 to a logical 0 The level interrupts are not latched. This means that if the pin is a logical 1 and the level high interrupt is active, it will become inactive as soon as the pin changes to a logical 0. The edge interrupts are stored in the INTR register and can be cleared by writing to the INTR register.