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dreq_num_rp2350 enum
Syntax
enum dreq_num_rp2350
{
DREQ_PIO0_TX0 = 0,
DREQ_PIO0_TX1 = 1,
DREQ_PIO0_TX2 = 2,
DREQ_PIO0_TX3 = 3,
DREQ_PIO0_RX0 = 4,
DREQ_PIO0_RX1 = 5,
DREQ_PIO0_RX2 = 6,
DREQ_PIO0_RX3 = 7,
DREQ_PIO1_TX0 = 8,
DREQ_PIO1_TX1 = 9,
DREQ_PIO1_TX2 = 10,
DREQ_PIO1_TX3 = 11,
DREQ_PIO1_RX0 = 12,
DREQ_PIO1_RX1 = 13,
DREQ_PIO1_RX2 = 14,
DREQ_PIO1_RX3 = 15,
DREQ_PIO2_TX0 = 16,
DREQ_PIO2_TX1 = 17,
DREQ_PIO2_TX2 = 18,
DREQ_PIO2_TX3 = 19,
DREQ_PIO2_RX0 = 20,
DREQ_PIO2_RX1 = 21,
DREQ_PIO2_RX2 = 22,
DREQ_PIO2_RX3 = 23,
DREQ_SPI0_TX = 24,
DREQ_SPI0_RX = 25,
DREQ_SPI1_TX = 26,
DREQ_SPI1_RX = 27,
DREQ_UART0_TX = 28,
DREQ_UART0_RX = 29,
DREQ_UART1_TX = 30,
DREQ_UART1_RX = 31,
DREQ_PWM_WRAP0 = 32,
DREQ_PWM_WRAP1 = 33,
DREQ_PWM_WRAP2 = 34,
DREQ_PWM_WRAP3 = 35,
DREQ_PWM_WRAP4 = 36,
DREQ_PWM_WRAP5 = 37,
DREQ_PWM_WRAP6 = 38,
DREQ_PWM_WRAP7 = 39,
DREQ_PWM_WRAP8 = 40,
DREQ_PWM_WRAP9 = 41,
DREQ_PWM_WRAP10 = 42,
DREQ_PWM_WRAP11 = 43,
DREQ_I2C0_TX = 44,
DREQ_I2C0_RX = 45,
DREQ_I2C1_TX = 46,
DREQ_I2C1_RX = 47,
DREQ_ADC = 48,
DREQ_XIP_STREAM = 49,
DREQ_XIP_QMITX = 50,
DREQ_XIP_QMIRX = 51,
DREQ_HSTX = 52,
DREQ_CORESIGHT = 53,
DREQ_SHA256 = 54,
DREQ_DMA_TIMER0 = 59,
DREQ_DMA_TIMER1 = 60,
DREQ_DMA_TIMER2 = 61,
DREQ_DMA_TIMER3 = 62,
DREQ_FORCE = 63,
DREQ_COUNT
};
Values
Value
Declared as