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clock_dest_num_rp2350 enum
Syntax
enum clock_dest_num_rp2350
{
CLK_DEST_SYS_CLOCKS = 0,
CLK_DEST_SYS_ACCESSCTRL = 1,
CLK_DEST_ADC = 2,
CLK_DEST_SYS_ADC = 3,
CLK_DEST_SYS_BOOTRAM = 4,
CLK_DEST_SYS_BUSCTRL = 5,
CLK_DEST_SYS_BUSFABRIC = 6,
CLK_DEST_SYS_DMA = 7,
CLK_DEST_SYS_GLITCH_DETECTOR = 8,
CLK_DEST_HSTX = 9,
CLK_DEST_SYS_HSTX = 10,
CLK_DEST_SYS_I2C0 = 11,
CLK_DEST_SYS_I2C1 = 12,
CLK_DEST_SYS_IO = 13,
CLK_DEST_SYS_JTAG = 14,
CLK_DEST_REF_OTP = 15,
CLK_DEST_SYS_OTP = 16,
CLK_DEST_SYS_PADS = 17,
CLK_DEST_SYS_PIO0 = 18,
CLK_DEST_SYS_PIO1 = 19,
CLK_DEST_SYS_PIO2 = 20,
CLK_DEST_SYS_PLL_SYS = 21,
CLK_DEST_SYS_PLL_USB = 22,
CLK_DEST_REF_POWMAN = 23,
CLK_DEST_SYS_POWMAN = 24,
CLK_DEST_SYS_PWM = 25,
CLK_DEST_SYS_RESETS = 26,
CLK_DEST_SYS_ROM = 27,
CLK_DEST_SYS_ROSC = 28,
CLK_DEST_SYS_PSM = 29,
CLK_DEST_SYS_SHA256 = 30,
CLK_DEST_SYS_SIO = 31,
CLK_DEST_PERI_SPI0 = 32,
CLK_DEST_SYS_SPI0 = 33,
CLK_DEST_PERI_SPI1 = 34,
CLK_DEST_SYS_SPI1 = 35,
CLK_DEST_SYS_SRAM0 = 36,
CLK_DEST_SYS_SRAM1 = 37,
CLK_DEST_SYS_SRAM2 = 38,
CLK_DEST_SYS_SRAM3 = 39,
CLK_DEST_SYS_SRAM4 = 40,
CLK_DEST_SYS_SRAM5 = 41,
CLK_DEST_SYS_SRAM6 = 42,
CLK_DEST_SYS_SRAM7 = 43,
CLK_DEST_SYS_SRAM8 = 44,
CLK_DEST_SYS_SRAM9 = 45,
CLK_DEST_SYS_SYSCFG = 46,
CLK_DEST_SYS_SYSINFO = 47,
CLK_DEST_SYS_TBMAN = 48,
CLK_DEST_REF_TICKS = 49,
CLK_DEST_SYS_TICKS = 50,
CLK_DEST_SYS_TIMER0 = 51,
CLK_DEST_SYS_TIMER1 = 52,
CLK_DEST_SYS_TRNG = 53,
CLK_DEST_PERI_UART0 = 54,
CLK_DEST_SYS_UART0 = 55,
CLK_DEST_PERI_UART1 = 56,
CLK_DEST_SYS_UART1 = 57,
CLK_DEST_SYS_USBCTRL = 58,
CLK_DEST_USB = 59,
CLK_DEST_SYS_WATCHDOG = 60,
CLK_DEST_SYS_XIP = 61,
CLK_DEST_SYS_XOSC = 62,
NUM_CLOCK_DESTINATIONS
};
Values
Value
Declared as