src/rp2350/hardware_regs/include/hardware/regs/trng.h (PicoSDK)

Outline

#define _HARDWARE_REGS_TRNG_H

#define TRNG_RNG_IMR_OFFSET

#define TRNG_RNG_IMR_BITS

#define TRNG_RNG_IMR_RESET

#define TRNG_RNG_IMR_RESERVED_RESET

#define TRNG_RNG_IMR_RESERVED_BITS

#define TRNG_RNG_IMR_RESERVED_MSB

#define TRNG_RNG_IMR_RESERVED_LSB

#define TRNG_RNG_IMR_RESERVED_ACCESS

#define TRNG_RNG_IMR_VN_ERR_INT_MASK_RESET

#define TRNG_RNG_IMR_VN_ERR_INT_MASK_BITS

#define TRNG_RNG_IMR_VN_ERR_INT_MASK_MSB

#define TRNG_RNG_IMR_VN_ERR_INT_MASK_LSB

#define TRNG_RNG_IMR_VN_ERR_INT_MASK_ACCESS

#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_RESET

#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_BITS

#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_MSB

#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_LSB

#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_ACCESS

#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_RESET

#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_BITS

#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_MSB

#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_LSB

#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_ACCESS

#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_RESET

#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_BITS

#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_MSB

#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_LSB

#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_ACCESS

#define TRNG_RNG_ISR_OFFSET

#define TRNG_RNG_ISR_BITS

#define TRNG_RNG_ISR_RESET

#define TRNG_RNG_ISR_RESERVED_RESET

#define TRNG_RNG_ISR_RESERVED_BITS

#define TRNG_RNG_ISR_RESERVED_MSB

#define TRNG_RNG_ISR_RESERVED_LSB

#define TRNG_RNG_ISR_RESERVED_ACCESS

#define TRNG_RNG_ISR_VN_ERR_RESET

#define TRNG_RNG_ISR_VN_ERR_BITS

#define TRNG_RNG_ISR_VN_ERR_MSB

#define TRNG_RNG_ISR_VN_ERR_LSB

#define TRNG_RNG_ISR_VN_ERR_ACCESS

#define TRNG_RNG_ISR_CRNGT_ERR_RESET

#define TRNG_RNG_ISR_CRNGT_ERR_BITS

#define TRNG_RNG_ISR_CRNGT_ERR_MSB

#define TRNG_RNG_ISR_CRNGT_ERR_LSB

#define TRNG_RNG_ISR_CRNGT_ERR_ACCESS

#define TRNG_RNG_ISR_AUTOCORR_ERR_RESET

#define TRNG_RNG_ISR_AUTOCORR_ERR_BITS

#define TRNG_RNG_ISR_AUTOCORR_ERR_MSB

#define TRNG_RNG_ISR_AUTOCORR_ERR_LSB

#define TRNG_RNG_ISR_AUTOCORR_ERR_ACCESS

#define TRNG_RNG_ISR_EHR_VALID_RESET

#define TRNG_RNG_ISR_EHR_VALID_BITS

#define TRNG_RNG_ISR_EHR_VALID_MSB

#define TRNG_RNG_ISR_EHR_VALID_LSB

#define TRNG_RNG_ISR_EHR_VALID_ACCESS

#define TRNG_RNG_ICR_OFFSET

#define TRNG_RNG_ICR_BITS

#define TRNG_RNG_ICR_RESET

#define TRNG_RNG_ICR_RESERVED_RESET

#define TRNG_RNG_ICR_RESERVED_BITS

#define TRNG_RNG_ICR_RESERVED_MSB

#define TRNG_RNG_ICR_RESERVED_LSB

#define TRNG_RNG_ICR_RESERVED_ACCESS

#define TRNG_RNG_ICR_VN_ERR_RESET

#define TRNG_RNG_ICR_VN_ERR_BITS

#define TRNG_RNG_ICR_VN_ERR_MSB

#define TRNG_RNG_ICR_VN_ERR_LSB

#define TRNG_RNG_ICR_VN_ERR_ACCESS

#define TRNG_RNG_ICR_CRNGT_ERR_RESET

#define TRNG_RNG_ICR_CRNGT_ERR_BITS

#define TRNG_RNG_ICR_CRNGT_ERR_MSB

#define TRNG_RNG_ICR_CRNGT_ERR_LSB

#define TRNG_RNG_ICR_CRNGT_ERR_ACCESS

#define TRNG_RNG_ICR_AUTOCORR_ERR_RESET

#define TRNG_RNG_ICR_AUTOCORR_ERR_BITS

#define TRNG_RNG_ICR_AUTOCORR_ERR_MSB

#define TRNG_RNG_ICR_AUTOCORR_ERR_LSB

#define TRNG_RNG_ICR_AUTOCORR_ERR_ACCESS

#define TRNG_RNG_ICR_EHR_VALID_RESET

#define TRNG_RNG_ICR_EHR_VALID_BITS

#define TRNG_RNG_ICR_EHR_VALID_MSB

#define TRNG_RNG_ICR_EHR_VALID_LSB

#define TRNG_RNG_ICR_EHR_VALID_ACCESS

#define TRNG_TRNG_CONFIG_OFFSET

#define TRNG_TRNG_CONFIG_BITS

#define TRNG_TRNG_CONFIG_RESET

#define TRNG_TRNG_CONFIG_RESERVED_RESET

#define TRNG_TRNG_CONFIG_RESERVED_BITS

#define TRNG_TRNG_CONFIG_RESERVED_MSB

#define TRNG_TRNG_CONFIG_RESERVED_LSB

#define TRNG_TRNG_CONFIG_RESERVED_ACCESS

#define TRNG_TRNG_CONFIG_RND_SRC_SEL_RESET

#define TRNG_TRNG_CONFIG_RND_SRC_SEL_BITS

#define TRNG_TRNG_CONFIG_RND_SRC_SEL_MSB

#define TRNG_TRNG_CONFIG_RND_SRC_SEL_LSB

#define TRNG_TRNG_CONFIG_RND_SRC_SEL_ACCESS

#define TRNG_TRNG_VALID_OFFSET

#define TRNG_TRNG_VALID_BITS

#define TRNG_TRNG_VALID_RESET

#define TRNG_TRNG_VALID_RESERVED_RESET

#define TRNG_TRNG_VALID_RESERVED_BITS

#define TRNG_TRNG_VALID_RESERVED_MSB

#define TRNG_TRNG_VALID_RESERVED_LSB

#define TRNG_TRNG_VALID_RESERVED_ACCESS

#define TRNG_TRNG_VALID_EHR_VALID_RESET

#define TRNG_TRNG_VALID_EHR_VALID_BITS

#define TRNG_TRNG_VALID_EHR_VALID_MSB

#define TRNG_TRNG_VALID_EHR_VALID_LSB

#define TRNG_TRNG_VALID_EHR_VALID_ACCESS

#define TRNG_EHR_DATA0_OFFSET

#define TRNG_EHR_DATA0_BITS

#define TRNG_EHR_DATA0_RESET

#define TRNG_EHR_DATA0_MSB

#define TRNG_EHR_DATA0_LSB

#define TRNG_EHR_DATA0_ACCESS

#define TRNG_EHR_DATA1_OFFSET

#define TRNG_EHR_DATA1_BITS

#define TRNG_EHR_DATA1_RESET

#define TRNG_EHR_DATA1_MSB

#define TRNG_EHR_DATA1_LSB

#define TRNG_EHR_DATA1_ACCESS

#define TRNG_EHR_DATA2_OFFSET

#define TRNG_EHR_DATA2_BITS

#define TRNG_EHR_DATA2_RESET

#define TRNG_EHR_DATA2_MSB

#define TRNG_EHR_DATA2_LSB

#define TRNG_EHR_DATA2_ACCESS

#define TRNG_EHR_DATA3_OFFSET

#define TRNG_EHR_DATA3_BITS

#define TRNG_EHR_DATA3_RESET

#define TRNG_EHR_DATA3_MSB

#define TRNG_EHR_DATA3_LSB

#define TRNG_EHR_DATA3_ACCESS

#define TRNG_EHR_DATA4_OFFSET

#define TRNG_EHR_DATA4_BITS

#define TRNG_EHR_DATA4_RESET

#define TRNG_EHR_DATA4_MSB

#define TRNG_EHR_DATA4_LSB

#define TRNG_EHR_DATA4_ACCESS

#define TRNG_EHR_DATA5_OFFSET

#define TRNG_EHR_DATA5_BITS

#define TRNG_EHR_DATA5_RESET

#define TRNG_EHR_DATA5_MSB

#define TRNG_EHR_DATA5_LSB

#define TRNG_EHR_DATA5_ACCESS

#define TRNG_RND_SOURCE_ENABLE_OFFSET

#define TRNG_RND_SOURCE_ENABLE_BITS

#define TRNG_RND_SOURCE_ENABLE_RESET

#define TRNG_RND_SOURCE_ENABLE_RESERVED_RESET

#define TRNG_RND_SOURCE_ENABLE_RESERVED_BITS

#define TRNG_RND_SOURCE_ENABLE_RESERVED_MSB

#define TRNG_RND_SOURCE_ENABLE_RESERVED_LSB

#define TRNG_RND_SOURCE_ENABLE_RESERVED_ACCESS

#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_RESET

#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_BITS

#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_MSB

#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_LSB

#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_ACCESS

#define TRNG_SAMPLE_CNT1_OFFSET

#define TRNG_SAMPLE_CNT1_BITS

#define TRNG_SAMPLE_CNT1_RESET

#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_RESET

#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_BITS

#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_MSB

#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_LSB

#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_ACCESS

#define TRNG_AUTOCORR_STATISTIC_OFFSET

#define TRNG_AUTOCORR_STATISTIC_BITS

#define TRNG_AUTOCORR_STATISTIC_RESET

#define TRNG_AUTOCORR_STATISTIC_RESERVED_RESET

#define TRNG_AUTOCORR_STATISTIC_RESERVED_BITS

#define TRNG_AUTOCORR_STATISTIC_RESERVED_MSB

#define TRNG_AUTOCORR_STATISTIC_RESERVED_LSB

#define TRNG_AUTOCORR_STATISTIC_RESERVED_ACCESS

#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_RESET

#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_BITS

#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_MSB

#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_LSB

#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_ACCESS

#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_RESET

#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_BITS

#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_MSB

#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_LSB

#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_ACCESS

#define TRNG_TRNG_DEBUG_CONTROL_OFFSET

#define TRNG_TRNG_DEBUG_CONTROL_BITS

#define TRNG_TRNG_DEBUG_CONTROL_RESET

#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_RESET

#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_BITS

#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_MSB

#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_LSB

#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_ACCESS

#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_RESET

#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_BITS

#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_MSB

#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_LSB

#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_ACCESS

#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_RESET

#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_BITS

#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_MSB

#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_LSB

#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_ACCESS

#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_RESET

#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_BITS

#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_MSB

#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_LSB

#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_ACCESS

#define TRNG_TRNG_SW_RESET_OFFSET

#define TRNG_TRNG_SW_RESET_BITS

#define TRNG_TRNG_SW_RESET_RESET

#define TRNG_TRNG_SW_RESET_RESERVED_RESET

#define TRNG_TRNG_SW_RESET_RESERVED_BITS

#define TRNG_TRNG_SW_RESET_RESERVED_MSB

#define TRNG_TRNG_SW_RESET_RESERVED_LSB

#define TRNG_TRNG_SW_RESET_RESERVED_ACCESS

#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_RESET

#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_BITS

#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_MSB

#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_LSB

#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_ACCESS

#define TRNG_RNG_DEBUG_EN_INPUT_OFFSET

#define TRNG_RNG_DEBUG_EN_INPUT_BITS

#define TRNG_RNG_DEBUG_EN_INPUT_RESET

#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_RESET

#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_BITS

#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_MSB

#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_LSB

#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_ACCESS

#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_RESET

#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_BITS

#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_MSB

#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_LSB

#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_ACCESS

#define TRNG_TRNG_BUSY_OFFSET

#define TRNG_TRNG_BUSY_BITS

#define TRNG_TRNG_BUSY_RESET

#define TRNG_TRNG_BUSY_RESERVED_RESET

#define TRNG_TRNG_BUSY_RESERVED_BITS

#define TRNG_TRNG_BUSY_RESERVED_MSB

#define TRNG_TRNG_BUSY_RESERVED_LSB

#define TRNG_TRNG_BUSY_RESERVED_ACCESS

#define TRNG_TRNG_BUSY_TRNG_BUSY_RESET

#define TRNG_TRNG_BUSY_TRNG_BUSY_BITS

#define TRNG_TRNG_BUSY_TRNG_BUSY_MSB

#define TRNG_TRNG_BUSY_TRNG_BUSY_LSB

#define TRNG_TRNG_BUSY_TRNG_BUSY_ACCESS

#define TRNG_RST_BITS_COUNTER_OFFSET

#define TRNG_RST_BITS_COUNTER_BITS

#define TRNG_RST_BITS_COUNTER_RESET

#define TRNG_RST_BITS_COUNTER_RESERVED_RESET

#define TRNG_RST_BITS_COUNTER_RESERVED_BITS

#define TRNG_RST_BITS_COUNTER_RESERVED_MSB

#define TRNG_RST_BITS_COUNTER_RESERVED_LSB

#define TRNG_RST_BITS_COUNTER_RESERVED_ACCESS

#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_RESET

#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_BITS

#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_MSB

#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_LSB

#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_ACCESS

#define TRNG_RNG_VERSION_OFFSET

#define TRNG_RNG_VERSION_BITS

#define TRNG_RNG_VERSION_RESET

#define TRNG_RNG_VERSION_RESERVED_RESET

#define TRNG_RNG_VERSION_RESERVED_BITS

#define TRNG_RNG_VERSION_RESERVED_MSB

#define TRNG_RNG_VERSION_RESERVED_LSB

#define TRNG_RNG_VERSION_RESERVED_ACCESS

#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_RESET

#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_BITS

#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_MSB

#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_LSB

#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_ACCESS

#define TRNG_RNG_VERSION_RESEEDING_EXISTS_RESET

#define TRNG_RNG_VERSION_RESEEDING_EXISTS_BITS

#define TRNG_RNG_VERSION_RESEEDING_EXISTS_MSB

#define TRNG_RNG_VERSION_RESEEDING_EXISTS_LSB

#define TRNG_RNG_VERSION_RESEEDING_EXISTS_ACCESS

#define TRNG_RNG_VERSION_KAT_EXISTS_RESET

#define TRNG_RNG_VERSION_KAT_EXISTS_BITS

#define TRNG_RNG_VERSION_KAT_EXISTS_MSB

#define TRNG_RNG_VERSION_KAT_EXISTS_LSB

#define TRNG_RNG_VERSION_KAT_EXISTS_ACCESS

#define TRNG_RNG_VERSION_PRNG_EXISTS_RESET

#define TRNG_RNG_VERSION_PRNG_EXISTS_BITS

#define TRNG_RNG_VERSION_PRNG_EXISTS_MSB

#define TRNG_RNG_VERSION_PRNG_EXISTS_LSB

#define TRNG_RNG_VERSION_PRNG_EXISTS_ACCESS

#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_RESET

#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_BITS

#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_MSB

#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_LSB

#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_ACCESS

#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_RESET

#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_BITS

#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_MSB

#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_LSB

#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_ACCESS

#define TRNG_RNG_VERSION_CRNGT_EXISTS_RESET

#define TRNG_RNG_VERSION_CRNGT_EXISTS_BITS

#define TRNG_RNG_VERSION_CRNGT_EXISTS_MSB

#define TRNG_RNG_VERSION_CRNGT_EXISTS_LSB

#define TRNG_RNG_VERSION_CRNGT_EXISTS_ACCESS

#define TRNG_RNG_VERSION_EHR_WIDTH_192_RESET

#define TRNG_RNG_VERSION_EHR_WIDTH_192_BITS

#define TRNG_RNG_VERSION_EHR_WIDTH_192_MSB

#define TRNG_RNG_VERSION_EHR_WIDTH_192_LSB

#define TRNG_RNG_VERSION_EHR_WIDTH_192_ACCESS

#define TRNG_RNG_BIST_CNTR_0_OFFSET

#define TRNG_RNG_BIST_CNTR_0_BITS

#define TRNG_RNG_BIST_CNTR_0_RESET

#define TRNG_RNG_BIST_CNTR_0_RESERVED_RESET

#define TRNG_RNG_BIST_CNTR_0_RESERVED_BITS

#define TRNG_RNG_BIST_CNTR_0_RESERVED_MSB

#define TRNG_RNG_BIST_CNTR_0_RESERVED_LSB

#define TRNG_RNG_BIST_CNTR_0_RESERVED_ACCESS

#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_RESET

#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_BITS

#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_MSB

#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_LSB

#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_ACCESS

#define TRNG_RNG_BIST_CNTR_1_OFFSET

#define TRNG_RNG_BIST_CNTR_1_BITS

#define TRNG_RNG_BIST_CNTR_1_RESET

#define TRNG_RNG_BIST_CNTR_1_RESERVED_RESET

#define TRNG_RNG_BIST_CNTR_1_RESERVED_BITS

#define TRNG_RNG_BIST_CNTR_1_RESERVED_MSB

#define TRNG_RNG_BIST_CNTR_1_RESERVED_LSB

#define TRNG_RNG_BIST_CNTR_1_RESERVED_ACCESS

#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_RESET

#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_BITS

#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_MSB

#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_LSB

#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_ACCESS

#define TRNG_RNG_BIST_CNTR_2_OFFSET

#define TRNG_RNG_BIST_CNTR_2_BITS

#define TRNG_RNG_BIST_CNTR_2_RESET

#define TRNG_RNG_BIST_CNTR_2_RESERVED_RESET

#define TRNG_RNG_BIST_CNTR_2_RESERVED_BITS

#define TRNG_RNG_BIST_CNTR_2_RESERVED_MSB

#define TRNG_RNG_BIST_CNTR_2_RESERVED_LSB

#define TRNG_RNG_BIST_CNTR_2_RESERVED_ACCESS

#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_RESET

#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_BITS

#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_MSB

#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_LSB

#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_ACCESS

Files

SourceVuRaspberry Pi Pico SDK and ExamplesPicoSDKsrc/rp2350/hardware_regs/include/hardware/regs/trng.h

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

307

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

352

353

354

355

356

357

358

359

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

385

386

387

388

389

390

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

408

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

424

425

426

427

428

429

430

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

449

450

451

452

453

454

455

456

457

458

459

460

461

462

463

464

465

466

467

468

469

470

471

472

473

474

475

476

477

478

479

480

481

482

483

484

485

486

487

488

489

490

491

492

493

494

495

496

497

498

499

500

501

502

503

504

505

506

507

508

509

510

511

512

513

514

515

516

517

518

519

520

521

522

523

524

525

526

527

528

529

530

531

532

533

534

535

536

537

538

539

540

541

542

543

544

545

546

547

548

549

550

551

552

553

554

555

556

557

558

559

560

561

562

563

564

565

566

567

568

569

570

571

572

573

574

575

576

577

578

579

580

581

582

583

584

585

586

587

588

589

590

591

592

593

594

595

596

597

598

599

600

601

602

603

604

605

606

607

608

609

610

611

612

613

614

615

616

617

618

619

620

621

622

623

624

625

// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT /** * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ // ============================================================================= // Register block : TRNG // Version : 1 // Bus type : apb // Description : ARM TrustZone RNG register block // ============================================================================= #ifndef _HARDWARE_REGS_TRNG_H #define _HARDWARE_REGS_TRNG_H // ============================================================================= // Register : TRNG_RNG_IMR // Description : Interrupt masking. #define TRNG_RNG_IMR_OFFSET _u(0x00000100) #define TRNG_RNG_IMR_BITS _u(0xffffffff) #define TRNG_RNG_IMR_RESET _u(0x0000000f) // ----------------------------------------------------------------------------- // Field : TRNG_RNG_IMR_RESERVED // Description : RESERVED #define TRNG_RNG_IMR_RESERVED_RESET _u(0x0000000) #define TRNG_RNG_IMR_RESERVED_BITS _u(0xfffffff0) #define TRNG_RNG_IMR_RESERVED_MSB _u(31) #define TRNG_RNG_IMR_RESERVED_LSB _u(4) #define TRNG_RNG_IMR_RESERVED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_IMR_VN_ERR_INT_MASK // Description : 1'b1-mask interrupt, no interrupt will be generated. See // RNG_ISR for an explanation on this interrupt. #define TRNG_RNG_IMR_VN_ERR_INT_MASK_RESET _u(0x1) #define TRNG_RNG_IMR_VN_ERR_INT_MASK_BITS _u(0x00000008) #define TRNG_RNG_IMR_VN_ERR_INT_MASK_MSB _u(3) #define TRNG_RNG_IMR_VN_ERR_INT_MASK_LSB _u(3) #define TRNG_RNG_IMR_VN_ERR_INT_MASK_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_IMR_CRNGT_ERR_INT_MASK // Description : 1'b1-mask interrupt, no interrupt will be generated. See // RNG_ISR for an explanation on this interrupt. #define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_RESET _u(0x1) #define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_BITS _u(0x00000004) #define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_MSB _u(2) #define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_LSB _u(2) #define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK // Description : 1'b1-mask interrupt, no interrupt will be generated. See // RNG_ISR for an explanation on this interrupt. #define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_RESET _u(0x1) #define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_BITS _u(0x00000002) #define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_MSB _u(1) #define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_LSB _u(1) #define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_IMR_EHR_VALID_INT_MASK // Description : 1'b1-mask interrupt, no interrupt will be generated. See // RNG_ISR for an explanation on this interrupt. #define TRNG_RNG_IMR_EHR_VALID_INT_MASK_RESET _u(0x1) #define TRNG_RNG_IMR_EHR_VALID_INT_MASK_BITS _u(0x00000001) #define TRNG_RNG_IMR_EHR_VALID_INT_MASK_MSB _u(0) #define TRNG_RNG_IMR_EHR_VALID_INT_MASK_LSB _u(0) #define TRNG_RNG_IMR_EHR_VALID_INT_MASK_ACCESS "RW" // ============================================================================= // Register : TRNG_RNG_ISR // Description : RNG status register. If corresponding RNG_IMR bit is unmasked, // an interrupt will be generated. #define TRNG_RNG_ISR_OFFSET _u(0x00000104) #define TRNG_RNG_ISR_BITS _u(0xffffffff) #define TRNG_RNG_ISR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TRNG_RNG_ISR_RESERVED // Description : RESERVED #define TRNG_RNG_ISR_RESERVED_RESET _u(0x0000000) #define TRNG_RNG_ISR_RESERVED_BITS _u(0xfffffff0) #define TRNG_RNG_ISR_RESERVED_MSB _u(31) #define TRNG_RNG_ISR_RESERVED_LSB _u(4) #define TRNG_RNG_ISR_RESERVED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_ISR_VN_ERR // Description : 1'b1 indicates Von Neuman error. Error in von Neuman occurs if // 32 consecutive collected bits are identical, ZERO or ONE. #define TRNG_RNG_ISR_VN_ERR_RESET _u(0x0) #define TRNG_RNG_ISR_VN_ERR_BITS _u(0x00000008) #define TRNG_RNG_ISR_VN_ERR_MSB _u(3) #define TRNG_RNG_ISR_VN_ERR_LSB _u(3) #define TRNG_RNG_ISR_VN_ERR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_ISR_CRNGT_ERR // Description : 1'b1 indicates CRNGT in the RNG test failed. Failure occurs // when two consecutive blocks of 16 collected bits are equal. #define TRNG_RNG_ISR_CRNGT_ERR_RESET _u(0x0) #define TRNG_RNG_ISR_CRNGT_ERR_BITS _u(0x00000004) #define TRNG_RNG_ISR_CRNGT_ERR_MSB _u(2) #define TRNG_RNG_ISR_CRNGT_ERR_LSB _u(2) #define TRNG_RNG_ISR_CRNGT_ERR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_ISR_AUTOCORR_ERR // Description : 1'b1 indicates Autocorrelation test failed four times in a row. // When set, RNG cease from functioning until next reset. #define TRNG_RNG_ISR_AUTOCORR_ERR_RESET _u(0x0) #define TRNG_RNG_ISR_AUTOCORR_ERR_BITS _u(0x00000002) #define TRNG_RNG_ISR_AUTOCORR_ERR_MSB _u(1) #define TRNG_RNG_ISR_AUTOCORR_ERR_LSB _u(1) #define TRNG_RNG_ISR_AUTOCORR_ERR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_ISR_EHR_VALID // Description : 1'b1 indicates that 192 bits have been collected in the RNG, // and are ready to be read. #define TRNG_RNG_ISR_EHR_VALID_RESET _u(0x0) #define TRNG_RNG_ISR_EHR_VALID_BITS _u(0x00000001) #define TRNG_RNG_ISR_EHR_VALID_MSB _u(0) #define TRNG_RNG_ISR_EHR_VALID_LSB _u(0) #define TRNG_RNG_ISR_EHR_VALID_ACCESS "RO" // ============================================================================= // Register : TRNG_RNG_ICR // Description : Interrupt/status bit clear Register. #define TRNG_RNG_ICR_OFFSET _u(0x00000108) #define TRNG_RNG_ICR_BITS _u(0xffffffff) #define TRNG_RNG_ICR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TRNG_RNG_ICR_RESERVED // Description : RESERVED #define TRNG_RNG_ICR_RESERVED_RESET _u(0x0000000) #define TRNG_RNG_ICR_RESERVED_BITS _u(0xfffffff0) #define TRNG_RNG_ICR_RESERVED_MSB _u(31) #define TRNG_RNG_ICR_RESERVED_LSB _u(4) #define TRNG_RNG_ICR_RESERVED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_ICR_VN_ERR // Description : Write 1'b1 - clear corresponding bit in RNG_ISR. #define TRNG_RNG_ICR_VN_ERR_RESET _u(0x0) #define TRNG_RNG_ICR_VN_ERR_BITS _u(0x00000008) #define TRNG_RNG_ICR_VN_ERR_MSB _u(3) #define TRNG_RNG_ICR_VN_ERR_LSB _u(3) #define TRNG_RNG_ICR_VN_ERR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_ICR_CRNGT_ERR // Description : Write 1'b1 - clear corresponding bit in RNG_ISR. #define TRNG_RNG_ICR_CRNGT_ERR_RESET _u(0x0) #define TRNG_RNG_ICR_CRNGT_ERR_BITS _u(0x00000004) #define TRNG_RNG_ICR_CRNGT_ERR_MSB _u(2) #define TRNG_RNG_ICR_CRNGT_ERR_LSB _u(2) #define TRNG_RNG_ICR_CRNGT_ERR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_ICR_AUTOCORR_ERR // Description : Cannot be cleared by SW! Only RNG reset clears this bit. #define TRNG_RNG_ICR_AUTOCORR_ERR_RESET _u(0x0) #define TRNG_RNG_ICR_AUTOCORR_ERR_BITS _u(0x00000002) #define TRNG_RNG_ICR_AUTOCORR_ERR_MSB _u(1) #define TRNG_RNG_ICR_AUTOCORR_ERR_LSB _u(1) #define TRNG_RNG_ICR_AUTOCORR_ERR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_ICR_EHR_VALID // Description : Write 1'b1 - clear corresponding bit in RNG_ISR. #define TRNG_RNG_ICR_EHR_VALID_RESET _u(0x0) #define TRNG_RNG_ICR_EHR_VALID_BITS _u(0x00000001) #define TRNG_RNG_ICR_EHR_VALID_MSB _u(0) #define TRNG_RNG_ICR_EHR_VALID_LSB _u(0) #define TRNG_RNG_ICR_EHR_VALID_ACCESS "RW" // ============================================================================= // Register : TRNG_TRNG_CONFIG // Description : Selecting the inverter-chain length. #define TRNG_TRNG_CONFIG_OFFSET _u(0x0000010c) #define TRNG_TRNG_CONFIG_BITS _u(0xffffffff) #define TRNG_TRNG_CONFIG_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TRNG_TRNG_CONFIG_RESERVED // Description : RESERVED #define TRNG_TRNG_CONFIG_RESERVED_RESET _u(0x00000000) #define TRNG_TRNG_CONFIG_RESERVED_BITS _u(0xfffffffc) #define TRNG_TRNG_CONFIG_RESERVED_MSB _u(31) #define TRNG_TRNG_CONFIG_RESERVED_LSB _u(2) #define TRNG_TRNG_CONFIG_RESERVED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_TRNG_CONFIG_RND_SRC_SEL // Description : Selects the number of inverters (out of four possible // selections) in the ring oscillator (the entropy source). #define TRNG_TRNG_CONFIG_RND_SRC_SEL_RESET _u(0x0) #define TRNG_TRNG_CONFIG_RND_SRC_SEL_BITS _u(0x00000003) #define TRNG_TRNG_CONFIG_RND_SRC_SEL_MSB _u(1) #define TRNG_TRNG_CONFIG_RND_SRC_SEL_LSB _u(0) #define TRNG_TRNG_CONFIG_RND_SRC_SEL_ACCESS "RW" // ============================================================================= // Register : TRNG_TRNG_VALID // Description : 192 bit collection indication. #define TRNG_TRNG_VALID_OFFSET _u(0x00000110) #define TRNG_TRNG_VALID_BITS _u(0xffffffff) #define TRNG_TRNG_VALID_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TRNG_TRNG_VALID_RESERVED // Description : RESERVED #define TRNG_TRNG_VALID_RESERVED_RESET _u(0x00000000) #define TRNG_TRNG_VALID_RESERVED_BITS _u(0xfffffffe) #define TRNG_TRNG_VALID_RESERVED_MSB _u(31) #define TRNG_TRNG_VALID_RESERVED_LSB _u(1) #define TRNG_TRNG_VALID_RESERVED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_TRNG_VALID_EHR_VALID // Description : 1'b1 indicates that collection of bits in the RNG is completed, // and data can be read from EHR_DATA register. #define TRNG_TRNG_VALID_EHR_VALID_RESET _u(0x0) #define TRNG_TRNG_VALID_EHR_VALID_BITS _u(0x00000001) #define TRNG_TRNG_VALID_EHR_VALID_MSB _u(0) #define TRNG_TRNG_VALID_EHR_VALID_LSB _u(0) #define TRNG_TRNG_VALID_EHR_VALID_ACCESS "RO" // ============================================================================= // Register : TRNG_EHR_DATA0 // Description : RNG collected bits. // Bits [31:0] of Entropy Holding Register (EHR) - RNG output // register #define TRNG_EHR_DATA0_OFFSET _u(0x00000114) #define TRNG_EHR_DATA0_BITS _u(0xffffffff) #define TRNG_EHR_DATA0_RESET _u(0x00000000) #define TRNG_EHR_DATA0_MSB _u(31) #define TRNG_EHR_DATA0_LSB _u(0) #define TRNG_EHR_DATA0_ACCESS "RO" // ============================================================================= // Register : TRNG_EHR_DATA1 // Description : RNG collected bits. // Bits [63:32] of Entropy Holding Register (EHR) - RNG output // register #define TRNG_EHR_DATA1_OFFSET _u(0x00000118) #define TRNG_EHR_DATA1_BITS _u(0xffffffff) #define TRNG_EHR_DATA1_RESET _u(0x00000000) #define TRNG_EHR_DATA1_MSB _u(31) #define TRNG_EHR_DATA1_LSB _u(0) #define TRNG_EHR_DATA1_ACCESS "RO" // ============================================================================= // Register : TRNG_EHR_DATA2 // Description : RNG collected bits. // Bits [95:64] of Entropy Holding Register (EHR) - RNG output // register #define TRNG_EHR_DATA2_OFFSET _u(0x0000011c) #define TRNG_EHR_DATA2_BITS _u(0xffffffff) #define TRNG_EHR_DATA2_RESET _u(0x00000000) #define TRNG_EHR_DATA2_MSB _u(31) #define TRNG_EHR_DATA2_LSB _u(0) #define TRNG_EHR_DATA2_ACCESS "RO" // ============================================================================= // Register : TRNG_EHR_DATA3 // Description : RNG collected bits. // Bits [127:96] of Entropy Holding Register (EHR) - RNG output // register #define TRNG_EHR_DATA3_OFFSET _u(0x00000120) #define TRNG_EHR_DATA3_BITS _u(0xffffffff) #define TRNG_EHR_DATA3_RESET _u(0x00000000) #define TRNG_EHR_DATA3_MSB _u(31) #define TRNG_EHR_DATA3_LSB _u(0) #define TRNG_EHR_DATA3_ACCESS "RO" // ============================================================================= // Register : TRNG_EHR_DATA4 // Description : RNG collected bits. // Bits [159:128] of Entropy Holding Register (EHR) - RNG output // register #define TRNG_EHR_DATA4_OFFSET _u(0x00000124) #define TRNG_EHR_DATA4_BITS _u(0xffffffff) #define TRNG_EHR_DATA4_RESET _u(0x00000000) #define TRNG_EHR_DATA4_MSB _u(31) #define TRNG_EHR_DATA4_LSB _u(0) #define TRNG_EHR_DATA4_ACCESS "RO" // ============================================================================= // Register : TRNG_EHR_DATA5 // Description : RNG collected bits. // Bits [191:160] of Entropy Holding Register (EHR) - RNG output // register #define TRNG_EHR_DATA5_OFFSET _u(0x00000128) #define TRNG_EHR_DATA5_BITS _u(0xffffffff) #define TRNG_EHR_DATA5_RESET _u(0x00000000) #define TRNG_EHR_DATA5_MSB _u(31) #define TRNG_EHR_DATA5_LSB _u(0) #define TRNG_EHR_DATA5_ACCESS "RO" // ============================================================================= // Register : TRNG_RND_SOURCE_ENABLE // Description : Enable signal for the random source. #define TRNG_RND_SOURCE_ENABLE_OFFSET _u(0x0000012c) #define TRNG_RND_SOURCE_ENABLE_BITS _u(0xffffffff) #define TRNG_RND_SOURCE_ENABLE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TRNG_RND_SOURCE_ENABLE_RESERVED // Description : RESERVED #define TRNG_RND_SOURCE_ENABLE_RESERVED_RESET _u(0x00000000) #define TRNG_RND_SOURCE_ENABLE_RESERVED_BITS _u(0xfffffffe) #define TRNG_RND_SOURCE_ENABLE_RESERVED_MSB _u(31) #define TRNG_RND_SOURCE_ENABLE_RESERVED_LSB _u(1) #define TRNG_RND_SOURCE_ENABLE_RESERVED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RND_SOURCE_ENABLE_RND_SRC_EN // Description : * 1'b1 - entropy source is enabled. *1'b0 - entropy source is // disabled #define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_RESET _u(0x0) #define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_BITS _u(0x00000001) #define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_MSB _u(0) #define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_LSB _u(0) #define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_ACCESS "RW" // ============================================================================= // Register : TRNG_SAMPLE_CNT1 // Description : Counts clocks between sampling of random bit. #define TRNG_SAMPLE_CNT1_OFFSET _u(0x00000130) #define TRNG_SAMPLE_CNT1_BITS _u(0xffffffff) #define TRNG_SAMPLE_CNT1_RESET _u(0x0000ffff) // ----------------------------------------------------------------------------- // Field : TRNG_SAMPLE_CNT1_SAMPLE_CNTR1 // Description : Sets the number of rng_clk cycles between two consecutive ring // oscillator samples. Note! If the Von-Neuman is bypassed, the // minimum value for sample counter must not be less then decimal // seventeen #define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_RESET _u(0x0000ffff) #define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_BITS _u(0xffffffff) #define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_MSB _u(31) #define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_LSB _u(0) #define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_ACCESS "RW" // ============================================================================= // Register : TRNG_AUTOCORR_STATISTIC // Description : Statistic about Autocorrelation test activations. #define TRNG_AUTOCORR_STATISTIC_OFFSET _u(0x00000134) #define TRNG_AUTOCORR_STATISTIC_BITS _u(0xffffffff) #define TRNG_AUTOCORR_STATISTIC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TRNG_AUTOCORR_STATISTIC_RESERVED // Description : RESERVED #define TRNG_AUTOCORR_STATISTIC_RESERVED_RESET _u(0x000) #define TRNG_AUTOCORR_STATISTIC_RESERVED_BITS _u(0xffc00000) #define TRNG_AUTOCORR_STATISTIC_RESERVED_MSB _u(31) #define TRNG_AUTOCORR_STATISTIC_RESERVED_LSB _u(22) #define TRNG_AUTOCORR_STATISTIC_RESERVED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS // Description : Count each time an autocorrelation test fails. Any write to the // register reset the counter. Stop collecting statistic if one of // the counters reached the limit. #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_RESET _u(0x00) #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_BITS _u(0x003fc000) #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_MSB _u(21) #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_LSB _u(14) #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS // Description : Count each time an autocorrelation test starts. Any write to // the register reset the counter. Stop collecting statistic if // one of the counters reached the limit. #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_RESET _u(0x0000) #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_BITS _u(0x00003fff) #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_MSB _u(13) #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_LSB _u(0) #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_ACCESS "RW" // ============================================================================= // Register : TRNG_TRNG_DEBUG_CONTROL // Description : Debug register. #define TRNG_TRNG_DEBUG_CONTROL_OFFSET _u(0x00000138) #define TRNG_TRNG_DEBUG_CONTROL_BITS _u(0x0000000f) #define TRNG_TRNG_DEBUG_CONTROL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS // Description : When set, the autocorrelation test in the TRNG module is // bypassed. #define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_RESET _u(0x0) #define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_BITS _u(0x00000008) #define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_MSB _u(3) #define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_LSB _u(3) #define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS // Description : When set, the CRNGT test in the RNG is bypassed. #define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_RESET _u(0x0) #define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_BITS _u(0x00000004) #define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_MSB _u(2) #define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_LSB _u(2) #define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS // Description : When set, the Von-Neuman balancer is bypassed (including the 32 // consecutive bits test). #define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_RESET _u(0x0) #define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_BITS _u(0x00000002) #define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_MSB _u(1) #define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_LSB _u(1) #define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TRNG_TRNG_DEBUG_CONTROL_RESERVED // Description : N/A #define TRNG_TRNG_DEBUG_CONTROL_RESERVED_RESET _u(0x0) #define TRNG_TRNG_DEBUG_CONTROL_RESERVED_BITS _u(0x00000001) #define TRNG_TRNG_DEBUG_CONTROL_RESERVED_MSB _u(0) #define TRNG_TRNG_DEBUG_CONTROL_RESERVED_LSB _u(0) #define TRNG_TRNG_DEBUG_CONTROL_RESERVED_ACCESS "RO" // ============================================================================= // Register : TRNG_TRNG_SW_RESET // Description : Generate internal SW reset within the RNG block. #define TRNG_TRNG_SW_RESET_OFFSET _u(0x00000140) #define TRNG_TRNG_SW_RESET_BITS _u(0xffffffff) #define TRNG_TRNG_SW_RESET_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TRNG_TRNG_SW_RESET_RESERVED // Description : RESERVED #define TRNG_TRNG_SW_RESET_RESERVED_RESET _u(0x00000000) #define TRNG_TRNG_SW_RESET_RESERVED_BITS _u(0xfffffffe) #define TRNG_TRNG_SW_RESET_RESERVED_MSB _u(31) #define TRNG_TRNG_SW_RESET_RESERVED_LSB _u(1) #define TRNG_TRNG_SW_RESET_RESERVED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_TRNG_SW_RESET_TRNG_SW_RESET // Description : Writing 1'b1 to this register causes an internal RNG reset. #define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_RESET _u(0x0) #define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_BITS _u(0x00000001) #define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_MSB _u(0) #define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_LSB _u(0) #define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_ACCESS "RW" // ============================================================================= // Register : TRNG_RNG_DEBUG_EN_INPUT // Description : Enable the RNG debug mode #define TRNG_RNG_DEBUG_EN_INPUT_OFFSET _u(0x000001b4) #define TRNG_RNG_DEBUG_EN_INPUT_BITS _u(0xffffffff) #define TRNG_RNG_DEBUG_EN_INPUT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TRNG_RNG_DEBUG_EN_INPUT_RESERVED // Description : RESERVED #define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_RESET _u(0x00000000) #define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_BITS _u(0xfffffffe) #define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_MSB _u(31) #define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_LSB _u(1) #define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN // Description : * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled #define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_RESET _u(0x0) #define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_BITS _u(0x00000001) #define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_MSB _u(0) #define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_LSB _u(0) #define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_ACCESS "RW" // ============================================================================= // Register : TRNG_TRNG_BUSY // Description : RNG Busy indication. #define TRNG_TRNG_BUSY_OFFSET _u(0x000001b8) #define TRNG_TRNG_BUSY_BITS _u(0xffffffff) #define TRNG_TRNG_BUSY_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TRNG_TRNG_BUSY_RESERVED // Description : RESERVED #define TRNG_TRNG_BUSY_RESERVED_RESET _u(0x00000000) #define TRNG_TRNG_BUSY_RESERVED_BITS _u(0xfffffffe) #define TRNG_TRNG_BUSY_RESERVED_MSB _u(31) #define TRNG_TRNG_BUSY_RESERVED_LSB _u(1) #define TRNG_TRNG_BUSY_RESERVED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_TRNG_BUSY_TRNG_BUSY // Description : Reflects rng_busy status. #define TRNG_TRNG_BUSY_TRNG_BUSY_RESET _u(0x0) #define TRNG_TRNG_BUSY_TRNG_BUSY_BITS _u(0x00000001) #define TRNG_TRNG_BUSY_TRNG_BUSY_MSB _u(0) #define TRNG_TRNG_BUSY_TRNG_BUSY_LSB _u(0) #define TRNG_TRNG_BUSY_TRNG_BUSY_ACCESS "RO" // ============================================================================= // Register : TRNG_RST_BITS_COUNTER // Description : Reset the counter of collected bits in the RNG. #define TRNG_RST_BITS_COUNTER_OFFSET _u(0x000001bc) #define TRNG_RST_BITS_COUNTER_BITS _u(0xffffffff) #define TRNG_RST_BITS_COUNTER_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TRNG_RST_BITS_COUNTER_RESERVED // Description : RESERVED #define TRNG_RST_BITS_COUNTER_RESERVED_RESET _u(0x00000000) #define TRNG_RST_BITS_COUNTER_RESERVED_BITS _u(0xfffffffe) #define TRNG_RST_BITS_COUNTER_RESERVED_MSB _u(31) #define TRNG_RST_BITS_COUNTER_RESERVED_LSB _u(1) #define TRNG_RST_BITS_COUNTER_RESERVED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER // Description : Writing any value to this address will reset the bits counter // and RNG valid registers. RND_SORCE_ENABLE register must be // unset in order for the reset to take place. #define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_RESET _u(0x0) #define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_BITS _u(0x00000001) #define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_MSB _u(0) #define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_LSB _u(0) #define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_ACCESS "RW" // ============================================================================= // Register : TRNG_RNG_VERSION // Description : Displays the version settings of the TRNG. #define TRNG_RNG_VERSION_OFFSET _u(0x000001c0) #define TRNG_RNG_VERSION_BITS _u(0xffffffff) #define TRNG_RNG_VERSION_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TRNG_RNG_VERSION_RESERVED // Description : RESERVED #define TRNG_RNG_VERSION_RESERVED_RESET _u(0x000000) #define TRNG_RNG_VERSION_RESERVED_BITS _u(0xffffff00) #define TRNG_RNG_VERSION_RESERVED_MSB _u(31) #define TRNG_RNG_VERSION_RESERVED_LSB _u(8) #define TRNG_RNG_VERSION_RESERVED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_VERSION_RNG_USE_5_SBOXES // Description : * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES #define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_RESET _u(0x0) #define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_BITS _u(0x00000080) #define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_MSB _u(7) #define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_LSB _u(7) #define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_VERSION_RESEEDING_EXISTS // Description : * 1'b1 - Exists. *1'b0 - Does not exist #define TRNG_RNG_VERSION_RESEEDING_EXISTS_RESET _u(0x0) #define TRNG_RNG_VERSION_RESEEDING_EXISTS_BITS _u(0x00000040) #define TRNG_RNG_VERSION_RESEEDING_EXISTS_MSB _u(6) #define TRNG_RNG_VERSION_RESEEDING_EXISTS_LSB _u(6) #define TRNG_RNG_VERSION_RESEEDING_EXISTS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_VERSION_KAT_EXISTS // Description : * 1'b1 - Exists. *1'b0 - Does not exist #define TRNG_RNG_VERSION_KAT_EXISTS_RESET _u(0x0) #define TRNG_RNG_VERSION_KAT_EXISTS_BITS _u(0x00000020) #define TRNG_RNG_VERSION_KAT_EXISTS_MSB _u(5) #define TRNG_RNG_VERSION_KAT_EXISTS_LSB _u(5) #define TRNG_RNG_VERSION_KAT_EXISTS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_VERSION_PRNG_EXISTS // Description : * 1'b1 - Exists. *1'b0 - Does not exist #define TRNG_RNG_VERSION_PRNG_EXISTS_RESET _u(0x0) #define TRNG_RNG_VERSION_PRNG_EXISTS_BITS _u(0x00000010) #define TRNG_RNG_VERSION_PRNG_EXISTS_MSB _u(4) #define TRNG_RNG_VERSION_PRNG_EXISTS_LSB _u(4) #define TRNG_RNG_VERSION_PRNG_EXISTS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN // Description : * 1'b1 - Exists. *1'b0 - Does not exist #define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_RESET _u(0x0) #define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_BITS _u(0x00000008) #define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_MSB _u(3) #define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_LSB _u(3) #define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_VERSION_AUTOCORR_EXISTS // Description : * 1'b1 - Exists. *1'b0 - Does not exist #define TRNG_RNG_VERSION_AUTOCORR_EXISTS_RESET _u(0x0) #define TRNG_RNG_VERSION_AUTOCORR_EXISTS_BITS _u(0x00000004) #define TRNG_RNG_VERSION_AUTOCORR_EXISTS_MSB _u(2) #define TRNG_RNG_VERSION_AUTOCORR_EXISTS_LSB _u(2) #define TRNG_RNG_VERSION_AUTOCORR_EXISTS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_VERSION_CRNGT_EXISTS // Description : * 1'b1 - Exists. *1'b0 - Does not exist #define TRNG_RNG_VERSION_CRNGT_EXISTS_RESET _u(0x0) #define TRNG_RNG_VERSION_CRNGT_EXISTS_BITS _u(0x00000002) #define TRNG_RNG_VERSION_CRNGT_EXISTS_MSB _u(1) #define TRNG_RNG_VERSION_CRNGT_EXISTS_LSB _u(1) #define TRNG_RNG_VERSION_CRNGT_EXISTS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_VERSION_EHR_WIDTH_192 // Description : * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR #define TRNG_RNG_VERSION_EHR_WIDTH_192_RESET _u(0x0) #define TRNG_RNG_VERSION_EHR_WIDTH_192_BITS _u(0x00000001) #define TRNG_RNG_VERSION_EHR_WIDTH_192_MSB _u(0) #define TRNG_RNG_VERSION_EHR_WIDTH_192_LSB _u(0) #define TRNG_RNG_VERSION_EHR_WIDTH_192_ACCESS "RO" // ============================================================================= // Register : TRNG_RNG_BIST_CNTR_0 // Description : Collected BIST results. #define TRNG_RNG_BIST_CNTR_0_OFFSET _u(0x000001e0) #define TRNG_RNG_BIST_CNTR_0_BITS _u(0xffffffff) #define TRNG_RNG_BIST_CNTR_0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TRNG_RNG_BIST_CNTR_0_RESERVED // Description : RESERVED #define TRNG_RNG_BIST_CNTR_0_RESERVED_RESET _u(0x000) #define TRNG_RNG_BIST_CNTR_0_RESERVED_BITS _u(0xffc00000) #define TRNG_RNG_BIST_CNTR_0_RESERVED_MSB _u(31) #define TRNG_RNG_BIST_CNTR_0_RESERVED_LSB _u(22) #define TRNG_RNG_BIST_CNTR_0_RESERVED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL // Description : Reflects the results of RNG BIST counter. #define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_RESET _u(0x000000) #define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_BITS _u(0x003fffff) #define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_MSB _u(21) #define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_LSB _u(0) #define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_ACCESS "RO" // ============================================================================= // Register : TRNG_RNG_BIST_CNTR_1 // Description : Collected BIST results. #define TRNG_RNG_BIST_CNTR_1_OFFSET _u(0x000001e4) #define TRNG_RNG_BIST_CNTR_1_BITS _u(0xffffffff) #define TRNG_RNG_BIST_CNTR_1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TRNG_RNG_BIST_CNTR_1_RESERVED // Description : RESERVED #define TRNG_RNG_BIST_CNTR_1_RESERVED_RESET _u(0x000) #define TRNG_RNG_BIST_CNTR_1_RESERVED_BITS _u(0xffc00000) #define TRNG_RNG_BIST_CNTR_1_RESERVED_MSB _u(31) #define TRNG_RNG_BIST_CNTR_1_RESERVED_LSB _u(22) #define TRNG_RNG_BIST_CNTR_1_RESERVED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL // Description : Reflects the results of RNG BIST counter. #define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_RESET _u(0x000000) #define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_BITS _u(0x003fffff) #define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_MSB _u(21) #define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_LSB _u(0) #define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_ACCESS "RO" // ============================================================================= // Register : TRNG_RNG_BIST_CNTR_2 // Description : Collected BIST results. #define TRNG_RNG_BIST_CNTR_2_OFFSET _u(0x000001e8) #define TRNG_RNG_BIST_CNTR_2_BITS _u(0xffffffff) #define TRNG_RNG_BIST_CNTR_2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TRNG_RNG_BIST_CNTR_2_RESERVED // Description : RESERVED #define TRNG_RNG_BIST_CNTR_2_RESERVED_RESET _u(0x000) #define TRNG_RNG_BIST_CNTR_2_RESERVED_BITS _u(0xffc00000) #define TRNG_RNG_BIST_CNTR_2_RESERVED_MSB _u(31) #define TRNG_RNG_BIST_CNTR_2_RESERVED_LSB _u(22) #define TRNG_RNG_BIST_CNTR_2_RESERVED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL // Description : Reflects the results of RNG BIST counter. #define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_RESET _u(0x000000) #define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_BITS _u(0x003fffff) #define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_MSB _u(21) #define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_LSB _u(0) #define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_ACCESS "RO" // ============================================================================= #endif // _HARDWARE_REGS_TRNG_H

Details