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ulp_insn union
Instruction format structure All ULP instructions are 32 bit long. This union contains field layouts used by all of the supported instructions. This union also includes a special "macro" instruction layout. This is not a real instruction which can be executed by the CPU. It acts as a token which is removed from the program by the ulp_process_macros_and_load function. These structures are not intended to be used directly. Preprocessor definitions provided below fill the fields of these structure with the right arguments.
Syntax
union ulp_insn;
Implemented in ![]()
ulp.h:118
Fields
Field
Declared as
Description
Format of DELAY instruction.
Format of ST instruction.
Format of LD instruction.
Format of ALU instruction (both sources are registers).
Format of ALU instruction (stage counter and an immediate).
Format of RD_REG instruction.
Format of ADC instruction.
Format of BRANCH instruction (absolute address).
Format of BRANCH instruction (relative address, conditional on R0).
Format of BRANCH instruction (relative address, conditional on the stage counter).
Format of ALU instruction (one source is an immediate).
Format of WR_REG instruction.
struct {
uint32_t cycle_sel : 4;
uint32_t unused : 21;
uint32_t sub_opcode : 3;
uint32_t opcode : 4;
}
Format of END instruction with sleep.
struct {
uint32_t dreg : 2;
uint32_t label : 16;
uint32_t unused : 6;
uint32_t sub_opcode : 4;
uint32_t opcode: 4;
}
Format of tokens used by MACROs.
Format of TSENS instruction.
Format of I2C instruction.
Format of END instruction with wakeup.
Related Functions
Found 2 other functions taking a ulp_insn
argument:
Function
Description
Resolve all macro references in a program and load it into RTC memory