timg_wdtconfig3_reg_t::::wdt_stg1_hold field

wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727; Stage 1 timeout value, in MWDT clock cycles.

Syntax

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Summary

Declaration

uint32_t wdt_stg1_hold: 32;

Code

Location

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uint32_t wdt_stg1_hold: 32;

hw->wdtconfig3.wdt_stg1_hold = timeout;

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timg_wdtconfig3_reg_t::::wdt_stg1_hold is written by 1 function:

timg_wdtconfig3_reg_t::::wdt_stg1_hold

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