timg_wdtconfig0_reg_t::::wdt_stg2 field
wdt_stg2 : R/W; bitpos: [26:25]; default: 0; Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
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uint32_t wdt_stg2: 2;
timg_wdtconfig0_reg_t::::wdt_stg2 is written by 2 functions:
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timg_wdtconfig0_reg_t::
::wdt_stg2