timg_regclk_reg_t::::clk_en field

clk_en : R/W; bitpos: [31]; default: 0; Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software.

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Declaration

from timer_group_struct.h:686

uint32_t clk_en: 1;

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uint32_t clk_en: 1;

timer_group_struct.h:686

hw->regclk.clk_en = en;

timer_ll.h:317

timer_ll_enable_register_clock_always_on()

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timg_regclk_reg_t::::clk_en is written by 1 function:

timer_ll_enable_register_clock_always_on()

timg_regclk_reg_t::::clk_en

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