soc_clkout_sig_id_t - syntax, references, description

Values

Value

Declared as

Description

soc_clkout_sig_id_t::CLKOUT_SIG_I2S0

= 0

I2S0 clock, depends on the i2s driver configuration.

soc_clkout_sig_id_t::CLKOUT_SIG_PLL

= 1

PLL_CLK is the output of crystal oscillator frequency multiplier.

soc_clkout_sig_id_t::CLKOUT_SIG_RC_SLOW

= 4

RC slow clock, depends on the RTC_CLK_SRC configuration.

soc_clkout_sig_id_t::CLKOUT_SIG_XTAL

= 5

Main crystal oscillator clock.

soc_clkout_sig_id_t::CLKOUT_SIG_APLL

= 6

Divided by PLL, frequency is configurable.

soc_clkout_sig_id_t::CLKOUT_SIG_REF_TICK

= 12

Divided by APB clock, usually be 1MHz.

soc_clkout_sig_id_t::CLKOUT_SIG_PLL_F80M

= 13

From PLL, usually be 80MHz.

soc_clkout_sig_id_t::CLKOUT_SIG_RC_FAST

= 14

RC fast clock, about 8MHz.

soc_clkout_sig_id_t::CLKOUT_SIG_I2S1

= 15

I2S1 clock, depends on the i2s driver configuration.

soc_clkout_sig_id_t::CLKOUT_SIG_INVALID

= 0xFF

References

Code

Location

Scope

Referrer

typedef enum {

clk_tree_defs.h:463

} soc_clkout_sig_id_t;

clk_tree_defs.h:474

soc_clkout_sig_id_t

void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)

clk_tree_hal.c:112

clk_hal_clock_output_setup()

clk_hal_clock_output_setup()::clk_sig

void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id);

clk_tree_hal.h:69

clk_hal_clock_output_setup()

clk_hal_clock_output_setup()::clk_sig

soc_clkout_sig_id_t mapped_clock;

esp_clock_output.c:23

clkout_channel_handle

clkout_channel_handle::mapped_clock

static clkout_channel_handle_t* clkout_channel_alloc(soc_clkout_sig_id_t clk_sig, gpio_num_t gpio_num)

esp_clock_output.c:53

clkout_channel_alloc()

clkout_channel_alloc()::clk_sig

esp_err_t esp_clock_output_start(soc_clkout_sig_id_t clk_sig, gpio_num_t gpio_num, esp_clock_output_mapping_handle_t *clkout_mapping_ret_hdl)

esp_clock_output.c:196

esp_clock_output_start()

esp_clock_output_start()::clk_sig

esp_err_t esp_clock_output_start(soc_clkout_sig_id_t clk_sig, gpio_num_t gpio_num, esp_clock_output_mapping_handle_t *clkout_mapping_ret_hdl);

esp_clock_output.h:35

esp_clock_output_start()

esp_clock_output_start()::clk_sig

soc_clkout_sig_id_t clkout_sig = is_apll ? CLKOUT_SIG_APLL : (is_i2s0 ? CLKOUT_SIG_I2S0 : CLKOUT_SIG_I2S1);

i2s_common.c:910

i2s_check_set_mclk()

soc_clkout_sig_id_t clkout_sig = (i2s_num == I2S_NUM_0) ? CLKOUT_SIG_I2S0 : CLKOUT_SIG_I2S1;

i2s_legacy.c:1872

i2s_check_set_mclk()

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esp_clock_output_start()::clk_sig

esp_clock_output_start()

esp_clock_output.h:35

clk_hal_clock_output_setup()::clk_sig

clk_hal_clock_output_setup()

clk_tree_hal.h:69

clkout_channel_handle::mapped_clock

clkout_channel_handle

esp_clock_output.c:23

clkout_channel_alloc()::clk_sig

clkout_channel_alloc()

esp_clock_output.c:53

esp_clock_output_start()::clk_sig

esp_clock_output_start()

esp_clock_output.c:196

clk_hal_clock_output_setup()::clk_sig

clk_hal_clock_output_setup()

clk_tree_hal.c:112

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soc_clkout_sig_id_t enum

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