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SourceVuESP-IDF Framework and ExamplesESP-IDFsdmmc_hal_context_t::dev

sdmmc_hal_context_t::dev field

Syntax

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Summary

Declaration

from sdmmc_hal.h:27

sdmmc_soc_handle_t dev;

References

Code

Location

Referrer

sdmmc_soc_handle_t dev; // SDMMC SOC layer handle (i.e. register base address)

hal->dev = SDMMC_LL_GET_HW(0);

sdmmc_hal_init()

sdmmc_ll_reset_controller(s_host_ctx.hal.dev);

sdmmc_host.c:114

s_module_reset()

sdmmc_ll_reset_dma(s_host_ctx.hal.dev);

sdmmc_host.c:115

s_module_reset()

sdmmc_ll_reset_fifo(s_host_ctx.hal.dev);

sdmmc_host.c:116

s_module_reset()

bool is_done = sdmmc_ll_is_controller_reset_done(s_host_ctx.hal.dev) && sdmmc_ll_is_dma_reset_done(s_host_ctx.hal.dev) && sdmmc_ll_is_fifo_reset_done(s_host_ctx.hal.dev);

sdmmc_host.c:121

s_is_module_reset_done()

sdmmc_ll_set_clock_div(s_host_ctx.hal.dev, div);

sdmmc_host.c:175

sdmmc_host_set_clk_div()

sdmmc_ll_select_clk_source(s_host_ctx.hal.dev, src);

sdmmc_host.c:176

sdmmc_host_set_clk_div()

sdmmc_ll_init_phase_delay(s_host_ctx.hal.dev);

sdmmc_host.c:177

sdmmc_host_set_clk_div()

sdmmc_ll_set_data_timeout(s_host_ctx.hal.dev, data_timeout_cycles);

sdmmc_host.c:283

sdmmc_host_set_data_timeout()

sdmmc_ll_enable_card_clock(s_host_ctx.hal.dev, slot, false);

sdmmc_host.c:291

sdmmc_host_set_card_clk()

sdmmc_ll_set_card_clock_div(s_host_ctx.hal.dev, slot, card_div);

sdmmc_host.c:308

sdmmc_host_set_card_clk()

sdmmc_ll_enable_card_clock(s_host_ctx.hal.dev, slot, true);

sdmmc_host.c:318

sdmmc_host_set_card_clk()

sdmmc_ll_enable_card_clock_low_power(s_host_ctx.hal.dev, slot, true);

sdmmc_host.c:319

sdmmc_host_set_card_clk()

sdmmc_ll_set_response_timeout(s_host_ctx.hal.dev, 255);

sdmmc_host.c:329

sdmmc_host_set_card_clk()

int host_div = sdmmc_ll_get_clock_div(s_host_ctx.hal.dev);

sdmmc_host.c:347

sdmmc_host_get_real_freq()

int card_div = sdmmc_ll_get_card_clock_div(s_host_ctx.hal.dev, slot);

sdmmc_host.c:348

sdmmc_host_get_real_freq()

if (!sdmmc_ll_is_card_detected(s_host_ctx.hal.dev, slot) && !cmd.update_clk_reg) {

sdmmc_host.c:424

sdmmc_host_start_command()

if (cmd.data_expected && cmd.rw && sdmmc_ll_is_card_write_protected(s_host_ctx.hal.dev, slot)) {

sdmmc_host.c:427

sdmmc_host_start_command()

while (!(sdmmc_ll_is_command_taken(s_host_ctx.hal.dev))) {

sdmmc_host.c:438

sdmmc_host_start_command()

sdmmc_ll_set_command_arg(s_host_ctx.hal.dev, arg);

sdmmc_host.c:449

sdmmc_host_start_command()

sdmmc_ll_set_command(s_host_ctx.hal.dev, cmd);

sdmmc_host.c:452

sdmmc_host_start_command()

while (!(sdmmc_ll_is_command_taken(s_host_ctx.hal.dev))) {

sdmmc_host.c:454

sdmmc_host_start_command()

sdmmc_ll_clear_interrupt(s_host_ctx.hal.dev, 0xffffffff);

sdmmc_host.c:469

sdmmc_host_intmask_clear_disable()

sdmmc_ll_enable_interrupt(s_host_ctx.hal.dev, 0xffffffff, false);

sdmmc_host.c:470

sdmmc_host_intmask_clear_disable()

sdmmc_ll_enable_global_interrupt(s_host_ctx.hal.dev, false);

sdmmc_host.c:471

sdmmc_host_intmask_clear_disable()

sdmmc_ll_enable_interrupt(s_host_ctx.hal.dev, 0xffffffff, false);

sdmmc_host.c:476

sdmmc_host_intmask_set_enable()

sdmmc_ll_enable_interrupt(s_host_ctx.hal.dev, SDMMC_LL_EVENT_DEFAULT, true);

sdmmc_host.c:477

sdmmc_host_intmask_set_enable()

sdmmc_ll_enable_global_interrupt(s_host_ctx.hal.dev, true);

sdmmc_host.c:478

sdmmc_host_intmask_set_enable()

sdmmc_ll_enable_bus_clock(s_host_ctx.hal.dev, true);

sdmmc_host.c:490

sdmmc_host_init()

sdmmc_ll_reset_register(s_host_ctx.hal.dev);

sdmmc_host.c:491

sdmmc_host_init()

ESP_LOGD(TAG, "peripheral version %"PRIx32", hardware config %08"PRIx32, sdmmc_ll_get_version_id(s_host_ctx.hal.dev), sdmmc_ll_get_hw_config_info(s_host_ctx.hal.dev));

sdmmc_host.c:507

sdmmc_host_init()

sdmmc_ll_enable_busy_clear_interrupt(s_host_ctx.hal.dev, false);

sdmmc_host.c:536

sdmmc_host_init()

sdmmc_ll_init_dma(s_host_ctx.hal.dev);

sdmmc_host.c:539

sdmmc_host_init()

sdmmc_ll_deinit_clk(s_host_ctx.hal.dev);

sdmmc_host.c:830

sdmmc_host_deinit_internal()

sdmmc_ll_enable_bus_clock(s_host_ctx.hal.dev, false);

sdmmc_host.c:834

sdmmc_host_deinit_internal()

sdmmc_ll_set_clock_div(s_host_ctx.hal.dev, s_host_ctx.slot_ctx[slot].slot_host_div);

sdmmc_host.c:916

sdmmc_host_change_to_slot()

sdmmc_ll_set_card_width(s_host_ctx.hal.dev, slot, SD_BUS_WIDTH_1_BIT);

sdmmc_host.c:951

sdmmc_host_set_bus_width()

sdmmc_ll_set_card_width(s_host_ctx.hal.dev, slot, SD_BUS_WIDTH_4_BIT);

sdmmc_host.c:953

sdmmc_host_set_bus_width()

sdmmc_ll_set_card_width(s_host_ctx.hal.dev, slot, SD_BUS_WIDTH_8_BIT);

sdmmc_host.c:957

sdmmc_host_set_bus_width()

sdmmc_ll_enable_ddr_mode(s_host_ctx.hal.dev, slot, ddr_enabled);

sdmmc_host.c:983

sdmmc_host_set_bus_ddr_mode()

sdmmc_ll_enable_card_clock_low_power(s_host_ctx.hal.dev, slot, false);

sdmmc_host.c:994

sdmmc_host_set_cclk_always_on()

sdmmc_ll_enable_card_clock_low_power(s_host_ctx.hal.dev, slot, true);

sdmmc_host.c:996

sdmmc_host_set_cclk_always_on()

sdmmc_ll_enable_card_clock(s_host_ctx.hal.dev, slot, enable);

sdmmc_host.c:1004

sdmmc_host_enable_clk_cmd11()

sdmmc_ll_enable_1v8_mode(s_host_ctx.hal.dev, slot, enable);

sdmmc_host.c:1006

sdmmc_host_enable_clk_cmd11()

sdmmc_ll_stop_dma(s_host_ctx.hal.dev);

sdmmc_host.c:1011

sdmmc_host_dma_stop()

sdmmc_ll_set_data_transfer_len(s_host_ctx.hal.dev, data_size);

sdmmc_host.c:1017

sdmmc_host_dma_prepare()

sdmmc_ll_set_block_size(s_host_ctx.hal.dev, block_size);

sdmmc_host.c:1018

sdmmc_host_dma_prepare()

sdmmc_ll_set_desc_addr(s_host_ctx.hal.dev, (uint32_t)desc);

sdmmc_host.c:1019

sdmmc_host_dma_prepare()

sdmmc_ll_enable_dma(s_host_ctx.hal.dev, true);

sdmmc_host.c:1022

sdmmc_host_dma_prepare()

sdmmc_ll_poll_demand(s_host_ctx.hal.dev);

sdmmc_host.c:1028

sdmmc_host_dma_resume()

return sdmmc_ll_is_card_data_busy(s_host_ctx.hal.dev);

sdmmc_host.c:1033

sdmmc_host_card_busy()

sdmmc_ll_enable_interrupt(s_host_ctx.hal.dev, SDMMC_INTMASK_IO_SLOT0, false);

sdmmc_host.c:1055

sdmmc_host_io_int_wait()

sdmmc_ll_clear_interrupt(s_host_ctx.hal.dev, SDMMC_INTMASK_IO_SLOT0);

sdmmc_host.c:1056

sdmmc_host_io_int_wait()

sdmmc_ll_enable_interrupt(s_host_ctx.hal.dev, SDMMC_INTMASK_IO_SLOT1, false);

sdmmc_host.c:1058

sdmmc_host_io_int_wait()

sdmmc_ll_clear_interrupt(s_host_ctx.hal.dev, SDMMC_INTMASK_IO_SLOT1);

sdmmc_host.c:1059

sdmmc_host_io_int_wait()

sdmmc_ll_enable_interrupt(s_host_ctx.hal.dev, SDMMC_INTMASK_IO_SLOT0, true);

sdmmc_host.c:1071

sdmmc_host_io_int_wait()

sdmmc_ll_enable_interrupt(s_host_ctx.hal.dev, SDMMC_INTMASK_IO_SLOT1, true);

sdmmc_host.c:1073

sdmmc_host_io_int_wait()

uint32_t pending = sdmmc_ll_get_intr_status(s_host_ctx.hal.dev) & SDMMC_LL_SD_EVENT_MASK;

sdmmc_host.c:1105

sdmmc_ll_clear_interrupt(s_host_ctx.hal.dev, pending);

sdmmc_host.c:1106

uint32_t dma_pending = sdmmc_ll_get_idsts_interrupt_raw(s_host_ctx.hal.dev);

sdmmc_host.c:1109

sdmmc_ll_clear_idsts_interrupt(s_host_ctx.hal.dev, dma_pending);

sdmmc_host.c:1110

uint32_t sdio_pending = (sdmmc_ll_get_intr_status(s_host_ctx.hal.dev) & (SDMMC_INTMASK_IO_SLOT1 | SDMMC_INTMASK_IO_SLOT0));

sdmmc_host.c:1117

sdmmc_ll_enable_interrupt(s_host_ctx.hal.dev, sdio_pending, false);

sdmmc_host.c:1120

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Data Use

sdmmc_hal_context_t::dev is written by 1 function and is read by 22 functions:

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