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periph_interrput_t enum
Syntax
enum
{
ETS_WIFI_MAC_INTR_SOURCE = 0,
ETS_WIFI_MAC_NMI_SOURCE,
ETS_WIFI_BB_INTR_SOURCE,
ETS_BT_MAC_INTR_SOURCE,
ETS_BT_BB_INTR_SOURCE,
ETS_BT_BB_NMI_SOURCE,
ETS_RWBT_INTR_SOURCE,
ETS_RWBLE_INTR_SOURCE,
ETS_RWBT_NMI_SOURCE,
ETS_RWBLE_NMI_SOURCE,
ETS_SLC0_INTR_SOURCE,
ETS_SLC1_INTR_SOURCE,
ETS_UHCI0_INTR_SOURCE,
ETS_UHCI1_INTR_SOURCE,
ETS_TG0_T0_LEVEL_INTR_SOURCE,
ETS_TG0_T1_LEVEL_INTR_SOURCE,
ETS_TG0_WDT_LEVEL_INTR_SOURCE,
ETS_TG0_LACT_LEVEL_INTR_SOURCE,
ETS_TG1_T0_LEVEL_INTR_SOURCE,
ETS_TG1_T1_LEVEL_INTR_SOURCE,
ETS_TG1_WDT_LEVEL_INTR_SOURCE,
ETS_TG1_LACT_LEVEL_INTR_SOURCE,
ETS_GPIO_INTR_SOURCE,
ETS_GPIO_NMI_SOURCE,
ETS_FROM_CPU_INTR0_SOURCE,
ETS_FROM_CPU_INTR1_SOURCE,
ETS_FROM_CPU_INTR2_SOURCE,
ETS_FROM_CPU_INTR3_SOURCE,
ETS_SPI0_INTR_SOURCE,
ETS_SPI1_INTR_SOURCE,
ETS_SPI2_INTR_SOURCE,
ETS_SPI3_INTR_SOURCE,
ETS_I2S0_INTR_SOURCE,
ETS_I2S1_INTR_SOURCE,
ETS_UART0_INTR_SOURCE,
ETS_UART1_INTR_SOURCE,
ETS_UART2_INTR_SOURCE,
ETS_SDIO_HOST_INTR_SOURCE,
ETS_ETH_MAC_INTR_SOURCE,
ETS_PWM0_INTR_SOURCE,
ETS_PWM1_INTR_SOURCE,
ETS_LEDC_INTR_SOURCE = 43,
ETS_EFUSE_INTR_SOURCE,
ETS_TWAI_INTR_SOURCE,
ETS_RTC_CORE_INTR_SOURCE,
ETS_RMT_INTR_SOURCE,
ETS_PCNT_INTR_SOURCE,
ETS_I2C_EXT0_INTR_SOURCE,
ETS_I2C_EXT1_INTR_SOURCE,
ETS_RSA_INTR_SOURCE,
ETS_SPI1_DMA_INTR_SOURCE,
ETS_SPI2_DMA_INTR_SOURCE,
ETS_SPI3_DMA_INTR_SOURCE,
ETS_WDT_INTR_SOURCE,
ETS_TIMER1_INTR_SOURCE,
ETS_TIMER2_INTR_SOURCE,
ETS_TG0_T0_EDGE_INTR_SOURCE,
ETS_TG0_T1_EDGE_INTR_SOURCE,
ETS_TG0_WDT_EDGE_INTR_SOURCE,
ETS_TG0_LACT_EDGE_INTR_SOURCE,
ETS_TG1_T0_EDGE_INTR_SOURCE,
ETS_TG1_T1_EDGE_INTR_SOURCE,
ETS_TG1_WDT_EDGE_INTR_SOURCE,
ETS_TG1_LACT_EDGE_INTR_SOURCE,
ETS_MMU_IA_INTR_SOURCE,
ETS_MPU_IA_INTR_SOURCE,
ETS_CACHE_IA_INTR_SOURCE,
ETS_MAX_INTR_SOURCE,
};
Values
Value
Declared as
Description
interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI.
interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI.
interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission.
interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission.
interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission.
interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission.
interrupt of SPI0, level, SPI0 is for Cache Access, do not use this.
interrupt of SPI1, level, SPI1 is for flash read/write, do not use this.
interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this.