mcpwm_timer_cfg0_reg_t::::timer_prescale field

timer_prescale : R/W; bitpos: [7:0]; default: 0; Configure the divisor of PT0_clk, takes effect when PWM timer stops and starts agsin. period of PT0_clk = Period of PWM_clk * (PWM_TIMER_PRESCALE + 1)

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from mcpwm_struct.h:39

uint32_t timer_prescale: 8;

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uint32_t timer_prescale: 8;

mcpwm_struct.h:39

HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_prescale, prescale - 1);

mcpwm_ll.h:244

mcpwm_ll_timer_set_clock_prescale()

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mcpwm_timer_cfg0_reg_t::::timer_prescale is written by 1 function:

mcpwm_ll_timer_set_clock_prescale()

mcpwm_timer_cfg0_reg_t::::timer_prescale

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