mcpwm_fh_cfg1_reg_t::::fh_cbcpulse field

fh_cbcpulse : R/W; bitpos: [2:1]; default: 0; cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP, when bit0 and bit1 both set to 0: stop refresh, when bit0 and bit1 both set to 1: refresh at TEP/TEZ