mcpwm_clk_cfg_reg_t::::clk_prescale field

clk_prescale : R/W; bitpos: [7:0]; default: 0; Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)

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Declaration

uint32_t clk_prescale: 8;

Code

Location

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uint32_t clk_prescale: 8;

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mcpwm_clk_cfg_reg_t::::clk_prescale is written by 1 function:

mcpwm_clk_cfg_reg_t::::clk_prescale

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