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Summary Syntax References Data Use

SourceVuESP-IDF Framework and ExamplesESP-IDFEFUSE_BLK0

EFUSE_BLK0 value

Number of eFuse block. Reserved.

Syntax

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Summary

Declaration

from esp_efuse_chip.h:20

EFUSE_BLK0 = 0;

References

Code

Location

Referrer

EFUSE_BLK0 = 0, /**< Number of eFuse block. Reserved. */

esp_efuse_chip.h:20

if (blk == EFUSE_BLK0 || blk >= EFUSE_BLK_MAX || dst_key == NULL || size_bits == 0) {

esp_efuse_api.c:210

esp_efuse_read_block()

if (blk == EFUSE_BLK0 || blk >= EFUSE_BLK_MAX || src_key == NULL || size_bits == 0) {

esp_efuse_api.c:230

esp_efuse_write_block()

if (blk == EFUSE_BLK0 || blk >= EFUSE_BLK_MAX) {

esp_efuse_api_key.c:41

esp_efuse_set_write_protect()

if (blk == EFUSE_BLK0 || blk >= EFUSE_BLK_MAX) {

esp_efuse_api_key.c:51

esp_efuse_set_read_protect()

if (blk == EFUSE_BLK0) {

esp_efuse_api_key.c:62

esp_efuse_get_coding_scheme()

if (block == EFUSE_BLK0) {

esp_efuse_api_key.c:150

esp_efuse_get_key_purpose()

{EFUSE_BLK0, 0, 16}, // [] Efuse write disable mask,

esp_efuse_table.c:30

{EFUSE_BLK0, 0, 1}, // [WR_DIS.EFUSE_RD_DISABLE] wr_dis of RD_DIS,

esp_efuse_table.c:34

{EFUSE_BLK0, 1, 1}, // [] wr_dis of WR_DIS,

esp_efuse_table.c:38

{EFUSE_BLK0, 2, 1}, // [] wr_dis of FLASH_CRYPT_CNT,

esp_efuse_table.c:42

{EFUSE_BLK0, 2, 1}, // [] wr_dis of UART_DOWNLOAD_DIS,

esp_efuse_table.c:46

{EFUSE_BLK0, 3, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC,

esp_efuse_table.c:50

{EFUSE_BLK0, 3, 1}, // [WR_DIS.MAC_FACTORY_CRC] wr_dis of MAC_CRC,

esp_efuse_table.c:54

{EFUSE_BLK0, 3, 1}, // [WR_DIS.CHIP_VER_DIS_APP_CPU] wr_dis of DISABLE_APP_CPU,

esp_efuse_table.c:58

{EFUSE_BLK0, 3, 1}, // [WR_DIS.CHIP_VER_DIS_BT] wr_dis of DISABLE_BT,

esp_efuse_table.c:62

{EFUSE_BLK0, 3, 1}, // [WR_DIS.CHIP_VER_DIS_CACHE] wr_dis of DIS_CACHE,

esp_efuse_table.c:66

{EFUSE_BLK0, 3, 1}, // [] wr_dis of VOL_LEVEL_HP_INV,

esp_efuse_table.c:70

{EFUSE_BLK0, 4, 1}, // [WR_DIS.CK8M_FREQ] wr_dis of CLK8M_FREQ,

esp_efuse_table.c:74

{EFUSE_BLK0, 4, 1}, // [] wr_dis of ADC_VREF,

esp_efuse_table.c:78

{EFUSE_BLK0, 5, 1}, // [] wr_dis of XPD_SDIO_REG,

esp_efuse_table.c:82

{EFUSE_BLK0, 5, 1}, // [WR_DIS.SDIO_TIEH] wr_dis of XPD_SDIO_TIEH,

esp_efuse_table.c:86

{EFUSE_BLK0, 5, 1}, // [WR_DIS.SDIO_FORCE] wr_dis of XPD_SDIO_FORCE,

esp_efuse_table.c:90

{EFUSE_BLK0, 6, 1}, // [] wr_dis of SPI_PAD_CONFIG_CLK,

esp_efuse_table.c:94

{EFUSE_BLK0, 6, 1}, // [] wr_dis of SPI_PAD_CONFIG_Q,

esp_efuse_table.c:98

{EFUSE_BLK0, 6, 1}, // [] wr_dis of SPI_PAD_CONFIG_D,

esp_efuse_table.c:102

{EFUSE_BLK0, 6, 1}, // [] wr_dis of SPI_PAD_CONFIG_CS0,

esp_efuse_table.c:106

{EFUSE_BLK0, 7, 1}, // [WR_DIS.ENCRYPT_FLASH_KEY WR_DIS.BLK1] wr_dis of BLOCK1,

esp_efuse_table.c:110

{EFUSE_BLK0, 8, 1}, // [WR_DIS.SECURE_BOOT_KEY WR_DIS.BLK2] wr_dis of BLOCK2,

esp_efuse_table.c:114

{EFUSE_BLK0, 9, 1}, // [WR_DIS.BLK3] wr_dis of BLOCK3,

esp_efuse_table.c:118

{EFUSE_BLK0, 9, 1}, // [WR_DIS.MAC_CUSTOM_CRC] wr_dis of CUSTOM_MAC_CRC,

esp_efuse_table.c:122

{EFUSE_BLK0, 9, 1}, // [WR_DIS.MAC_CUSTOM] wr_dis of CUSTOM_MAC,

esp_efuse_table.c:126

{EFUSE_BLK0, 9, 1}, // [] wr_dis of ADC1_TP_LOW,

esp_efuse_table.c:130

{EFUSE_BLK0, 9, 1}, // [] wr_dis of ADC1_TP_HIGH,

esp_efuse_table.c:134

{EFUSE_BLK0, 9, 1}, // [] wr_dis of ADC2_TP_LOW,

esp_efuse_table.c:138

{EFUSE_BLK0, 9, 1}, // [] wr_dis of ADC2_TP_HIGH,

esp_efuse_table.c:142

{EFUSE_BLK0, 9, 1}, // [] wr_dis of SECURE_VERSION,

esp_efuse_table.c:146

{EFUSE_BLK0, 9, 1}, // [WR_DIS.MAC_CUSTOM_VER] wr_dis of MAC_VERSION,

esp_efuse_table.c:150

{EFUSE_BLK0, 10, 1}, // [] wr_dis of BLK3_PART_RESERVE,

esp_efuse_table.c:154

{EFUSE_BLK0, 10, 1}, // [WR_DIS.ENCRYPT_CONFIG] wr_dis of FLASH_CRYPT_CONFIG,

esp_efuse_table.c:158

{EFUSE_BLK0, 10, 1}, // [] wr_dis of CODING_SCHEME,

esp_efuse_table.c:162

{EFUSE_BLK0, 10, 1}, // [] wr_dis of KEY_STATUS,

esp_efuse_table.c:166

{EFUSE_BLK0, 12, 1}, // [] wr_dis of ABS_DONE_0,

esp_efuse_table.c:170

{EFUSE_BLK0, 13, 1}, // [] wr_dis of ABS_DONE_1,

esp_efuse_table.c:174

{EFUSE_BLK0, 14, 1}, // [WR_DIS.DISABLE_JTAG] wr_dis of JTAG_DISABLE,

esp_efuse_table.c:178

{EFUSE_BLK0, 15, 1}, // [] wr_dis of CONSOLE_DEBUG_DISABLE,

esp_efuse_table.c:182

{EFUSE_BLK0, 15, 1}, // [] wr_dis of DISABLE_DL_ENCRYPT,

esp_efuse_table.c:186

{EFUSE_BLK0, 15, 1}, // [] wr_dis of DISABLE_DL_DECRYPT,

esp_efuse_table.c:190

{EFUSE_BLK0, 15, 1}, // [] wr_dis of DISABLE_DL_CACHE,

esp_efuse_table.c:194

{EFUSE_BLK0, 16, 4}, // [] Disable reading from BlOCK1-3,

esp_efuse_table.c:198

{EFUSE_BLK0, 16, 1}, // [RD_DIS.ENCRYPT_FLASH_KEY RD_DIS.BLK1] rd_dis of BLOCK1,

esp_efuse_table.c:202

{EFUSE_BLK0, 17, 1}, // [RD_DIS.SECURE_BOOT_KEY RD_DIS.BLK2] rd_dis of BLOCK2,

esp_efuse_table.c:206

{EFUSE_BLK0, 18, 1}, // [RD_DIS.BLK3] rd_dis of BLOCK3,

esp_efuse_table.c:210

{EFUSE_BLK0, 18, 1}, // [RD_DIS.MAC_CUSTOM_CRC] rd_dis of CUSTOM_MAC_CRC,

esp_efuse_table.c:214

{EFUSE_BLK0, 18, 1}, // [RD_DIS.MAC_CUSTOM] rd_dis of CUSTOM_MAC,

esp_efuse_table.c:218

{EFUSE_BLK0, 18, 1}, // [] rd_dis of ADC1_TP_LOW,

esp_efuse_table.c:222

{EFUSE_BLK0, 18, 1}, // [] rd_dis of ADC1_TP_HIGH,

esp_efuse_table.c:226

{EFUSE_BLK0, 18, 1}, // [] rd_dis of ADC2_TP_LOW,

esp_efuse_table.c:230

{EFUSE_BLK0, 18, 1}, // [] rd_dis of ADC2_TP_HIGH,

esp_efuse_table.c:234

{EFUSE_BLK0, 18, 1}, // [] rd_dis of SECURE_VERSION,

esp_efuse_table.c:238

{EFUSE_BLK0, 18, 1}, // [RD_DIS.MAC_CUSTOM_VER] rd_dis of MAC_VERSION,

esp_efuse_table.c:242

{EFUSE_BLK0, 19, 1}, // [] rd_dis of BLK3_PART_RESERVE,

esp_efuse_table.c:246

{EFUSE_BLK0, 19, 1}, // [RD_DIS.ENCRYPT_CONFIG] rd_dis of FLASH_CRYPT_CONFIG,

esp_efuse_table.c:250

{EFUSE_BLK0, 19, 1}, // [] rd_dis of CODING_SCHEME,

esp_efuse_table.c:254

{EFUSE_BLK0, 19, 1}, // [] rd_dis of KEY_STATUS,

esp_efuse_table.c:258

{EFUSE_BLK0, 20, 7}, // [] Flash encryption is enabled if this field has an odd number of bits set,

esp_efuse_table.c:262

{EFUSE_BLK0, 27, 1}, // [] Disable UART download mode. Valid for ESP32 V3 and newer; only,

esp_efuse_table.c:266

{EFUSE_BLK0, 72, 8}, // [MAC_FACTORY] MAC address,

esp_efuse_table.c:270

{EFUSE_BLK0, 64, 8}, // [MAC_FACTORY] MAC address,

esp_efuse_table.c:271

{EFUSE_BLK0, 56, 8}, // [MAC_FACTORY] MAC address,

esp_efuse_table.c:272

{EFUSE_BLK0, 48, 8}, // [MAC_FACTORY] MAC address,

esp_efuse_table.c:273

{EFUSE_BLK0, 40, 8}, // [MAC_FACTORY] MAC address,

esp_efuse_table.c:274

{EFUSE_BLK0, 32, 8}, // [MAC_FACTORY] MAC address,

esp_efuse_table.c:275

{EFUSE_BLK0, 80, 8}, // [MAC_FACTORY_CRC] CRC8 for MAC address,

esp_efuse_table.c:279

{EFUSE_BLK0, 96, 1}, // [CHIP_VER_DIS_APP_CPU] Disables APP CPU,

esp_efuse_table.c:283

{EFUSE_BLK0, 97, 1}, // [CHIP_VER_DIS_BT] Disables Bluetooth,

esp_efuse_table.c:287

{EFUSE_BLK0, 98, 1}, // [CHIP_VER_PKG_4BIT] Chip package identifier #4bit,

esp_efuse_table.c:291

{EFUSE_BLK0, 99, 1}, // [CHIP_VER_DIS_CACHE] Disables cache,

esp_efuse_table.c:295

{EFUSE_BLK0, 100, 5}, // [] read for SPI_pad_config_hd,

esp_efuse_table.c:299

{EFUSE_BLK0, 105, 3}, // [CHIP_VER_PKG] Chip package identifier,

esp_efuse_table.c:303

{EFUSE_BLK0, 108, 1}, // [] If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise,

esp_efuse_table.c:307

{EFUSE_BLK0, 109, 1}, // [] If set; the ESP32's maximum CPU frequency has been rated,

esp_efuse_table.c:311

{EFUSE_BLK0, 110, 1}, // [] BLOCK3 partially served for ADC calibration data,

esp_efuse_table.c:315

{EFUSE_BLK0, 111, 1}, // [] bit is set to 1 for rev1 silicon,

esp_efuse_table.c:319

{EFUSE_BLK0, 128, 8}, // [CK8M_FREQ] 8MHz clock freq override,

esp_efuse_table.c:323

{EFUSE_BLK0, 136, 5}, // [] True ADC reference voltage,

esp_efuse_table.c:327

{EFUSE_BLK0, 142, 1}, // [] read for XPD_SDIO_REG,

esp_efuse_table.c:331

{EFUSE_BLK0, 143, 1}, // [SDIO_TIEH] If XPD_SDIO_FORCE & XPD_SDIO_REG {1: "3.3V"; 0: "1.8V"},

esp_efuse_table.c:335

{EFUSE_BLK0, 144, 1}, // [SDIO_FORCE] Ignore MTDI pin (GPIO12) for VDD_SDIO on reset,

esp_efuse_table.c:339

{EFUSE_BLK0, 160, 5}, // [] Override SD_CLK pad (GPIO6/SPICLK),

esp_efuse_table.c:343

{EFUSE_BLK0, 165, 5}, // [] Override SD_DATA_0 pad (GPIO7/SPIQ),

esp_efuse_table.c:347

{EFUSE_BLK0, 170, 5}, // [] Override SD_DATA_1 pad (GPIO8/SPID),

esp_efuse_table.c:351

{EFUSE_BLK0, 175, 5}, // [] Override SD_CMD pad (GPIO11/SPICS0),

esp_efuse_table.c:355

{EFUSE_BLK0, 180, 1}, // [],

esp_efuse_table.c:359

{EFUSE_BLK0, 182, 2}, // [] This field stores the voltage level for CPU to run at 240 MHz; or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO),

esp_efuse_table.c:363

{EFUSE_BLK0, 184, 2}, // [],

esp_efuse_table.c:367

{EFUSE_BLK0, 188, 4}, // [ENCRYPT_CONFIG] Flash encryption config (key tweak bits),

esp_efuse_table.c:371

{EFUSE_BLK0, 192, 2}, // [] Efuse variable block length scheme {0: "NONE (BLK1-3 len=256 bits)"; 1: "3/4 (BLK1-3 len=192 bits)"; 2: "REPEAT (BLK1-3 len=128 bits) not supported"; 3: "NONE (BLK1-3 len=256 bits)"},

esp_efuse_table.c:375

{EFUSE_BLK0, 194, 1}, // [] Disable ROM BASIC interpreter fallback,

esp_efuse_table.c:379

{EFUSE_BLK0, 195, 1}, // [],

esp_efuse_table.c:383

{EFUSE_BLK0, 196, 1}, // [] Secure boot V1 is enabled for bootloader image,

esp_efuse_table.c:387

{EFUSE_BLK0, 197, 1}, // [] Secure boot V2 is enabled for bootloader image,

esp_efuse_table.c:391

{EFUSE_BLK0, 198, 1}, // [DISABLE_JTAG] Disable JTAG,

esp_efuse_table.c:395

{EFUSE_BLK0, 199, 1}, // [] Disable flash encryption in UART bootloader,

esp_efuse_table.c:399

{EFUSE_BLK0, 200, 1}, // [] Disable flash decryption in UART bootloader,

esp_efuse_table.c:403

{EFUSE_BLK0, 201, 1}, // [] Disable flash cache in UART bootloader,

esp_efuse_table.c:407

{EFUSE_BLK0, 202, 1}, // [] Usage of efuse block 3 (reserved),

esp_efuse_table.c:411

{(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][6]},

esp_efuse_utility.c:34

for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {

esp_efuse_utility.c:84

esp_efuse_utility_burn_chip_opt()

for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {

esp_efuse_utility.c:99

esp_efuse_utility_burn_chip_opt()

for (int num_block = EFUSE_BLK0; num_block < EFUSE_BLK_MAX; num_block++) {

esp_efuse_utility.c:156

esp_efuse_utility_reset()

for (int num_block = EFUSE_BLK0; num_block < EFUSE_BLK_MAX; num_block++) {

esp_efuse_utility.c:208

esp_efuse_utility_update_virt_blocks()

for (int num_block = EFUSE_BLK0; num_block < EFUSE_BLK_MAX; num_block++) {

esp_efuse_utility.c:250

esp_efuse_utility_debug_dump_blocks()

Call Tree

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Data Use

EFUSE_BLK0 is read by 10 functions:

EFUSE_BLK0

esp_efuse_utility_burn_chip_opt()

esp_efuse_read_block()

esp_efuse_write_block()

esp_efuse_utility_reset()

esp_efuse_utility_update_virt_blocks()

esp_efuse_utility_debug_dump_blocks()

esp_efuse_set_write_protect()

esp_efuse_set_read_protect()

esp_efuse_get_coding_scheme()

esp_efuse_get_key_purpose()

Class Tree

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