clk_ll_rc_fast_d256_enable() function

Enable the output from the internal oscillator to be passed into a configurable divider, which by default divides the input clock frequency by 256. i.e. RC_FAST_D256_CLK = RC_FAST_CLK / 256 Divider values other than 256 may be configured, but this facility is not currently needed, so is not exposed in the code. The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions.