WRITE_PERI_REG - syntax, references, description

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Code

Location

#define WRITE_PERI_REG(addr, val) do { \

soc.h:113

WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD);

bootloader_random_esp32.c:53

WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD);

bootloader_random_esp32.c:54

WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD);

bootloader_random_esp32.c:55

WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD);

bootloader_random_esp32.c:56

WRITE_PERI_REG(RTC_XTAL_FREQ_REG, (xtal_freq_mhz & UINT16_MAX) | ((xtal_freq_mhz & UINT16_MAX) << 16));

clk_tree_ll.h:827

WRITE_PERI_REG(RTC_APB_FREQ_REG, (val & UINT16_MAX) | ((val & UINT16_MAX) << 16));

clk_tree_ll.h:861

WRITE_PERI_REG(SPI_W0_REG(spi_num) + i * 4, 0);

esp_psram_impl_quad.c:257

WRITE_PERI_REG(SPI_ADDR_REG(spi_num), *pInData->addr);

esp_psram_impl_quad.c:369

WRITE_PERI_REG(SPI_USER_REG(spi_num), backup_usr[spi_num]);

esp_psram_impl_quad.c:416

WRITE_PERI_REG(SPI_USER1_REG(spi_num), backup_usr1[spi_num]);

esp_psram_impl_quad.c:417

WRITE_PERI_REG(SPI_USER2_REG(spi_num), backup_usr2[spi_num]);

esp_psram_impl_quad.c:418

WRITE_PERI_REG(SPI_USER1_REG(spi_num), 0);

esp_psram_impl_quad.c:728

WRITE_PERI_REG(SPI_EXT3_REG(0), 0x1);

esp_psram_impl_quad.c:944

WRITE_PERI_REG(SPI_ADDR_REG(PSRAM_SPI_NUM), 32 << 24);

esp_psram_impl_quad.c:1017

WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_CE);

esp_rom_spiflash.c:119

WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff);

esp_rom_spiflash.c:140

WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_SE);

esp_rom_spiflash.c:141

WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff);

esp_rom_spiflash.c:156

WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_BE);

esp_rom_spiflash.c:157

WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, (temp_addr & 0xffffff) | ( ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM << ESP_ROM_SPIFLASH_BYTES_LEN )); // 32 byte a block

esp_rom_spiflash.c:195

WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4, *addr_source++);

esp_rom_spiflash.c:198

WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, (temp_addr & 0xffffff) | (temp_bl << ESP_ROM_SPIFLASH_BYTES_LEN ));

esp_rom_spiflash.c:203

WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4, *addr_source++);

esp_rom_spiflash.c:207

WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_PP);

esp_rom_spiflash.c:212

WRITE_PERI_REG(PERIPHS_SPI_FLASH_STATUS, 0); // clear regisrter

esp_rom_spiflash.c:228

WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_RDSR);

esp_rom_spiflash.c:229

WRITE_PERI_REG(PERIPHS_SPI_FLASH_STATUS, status_value); // write status regisrter

esp_rom_spiflash.c:259

WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_WRSR);

esp_rom_spiflash.c:260

WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8);

esp_rom_spiflash.c:291

WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8);

esp_rom_spiflash.c:303

WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_WREN); // enable write operation

esp_rom_spiflash.c:327

WRITE_PERI_REG(fifo_addr, ptr[i]);

i2c_ll.h:561

WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);

rtc_cntl_ll.h:21

WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);

rtc_cntl_ll.h:22

WRITE_PERI_REG(RTC_CNTL_SLP_REJECT_CONF_REG, reject_opt);

rtc_sleep.c:252

WRITE_PERI_REG(RTC_CNTL_SLP_REJECT_CONF_REG, reject_opt);

rtc_sleep.c:274

WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);

rtc_wdt.c:21

WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0);

rtc_wdt.c:26

WRITE_PERI_REG(get_addr_reg(stage), timeout);

rtc_wdt.c:97

WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \

soc.h:121

WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \

soc.h:127

WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \

soc.h:145

WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);

system_internal.c:116

WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);

system_internal.c:117

WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);

system_internal.c:118

WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);

system_internal.c:119

WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);

system_internal.c:120

WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);

system_internal.c:121

WRITE_PERI_REG(fifo_addr, buf[i]);

uart_ll.h:344

WRITE_PERI_REG macro

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