ESP-IDF
SPI_CACHE_SCTRL_REG
is only used within ESP-IDF.
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ESP-IDF Framework and Examples
ESP-IDF
SPI_CACHE_SCTRL_REG
SPI_CACHE_SCTRL_REG macro
Syntax
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Summary
Declaration
from
spi_reg.h:881
#define
SPI_CACHE_SCTRL_REG
(
i
)
(
REG_SPI_BASE
(
i
)
+
0x54
)
Arguments
Argument
i
Examples
References
from
examples
Code
Location
#define
SPI_CACHE_SCTRL_REG
(
i
)
(
REG_SPI_BASE
(
i
)
+
0x54
)
spi_reg.h:881
CLEAR_PERI_REG_MASK
(
SPI_CACHE_SCTRL_REG
(
0
)
,
SPI_USR_SRAM_DIO_M
)
;
//disable dio mode for cache command
esp_psram_impl_quad.c:1090
SET_PERI_REG_MASK
(
SPI_CACHE_SCTRL_REG
(
0
)
,
SPI_USR_SRAM_QIO_M
)
;
//enable qio mode for cache command
esp_psram_impl_quad.c:1091
SET_PERI_REG_MASK
(
SPI_CACHE_SCTRL_REG
(
0
)
,
SPI_CACHE_SRAM_USR_RCMD_M
)
;
//enable cache read command
esp_psram_impl_quad.c:1092
SET_PERI_REG_MASK
(
SPI_CACHE_SCTRL_REG
(
0
)
,
SPI_CACHE_SRAM_USR_WCMD_M
)
;
//enable cache write command
esp_psram_impl_quad.c:1093
SET_PERI_REG_BITS
(
SPI_CACHE_SCTRL_REG
(
0
)
,
SPI_SRAM_ADDR_BITLEN_V
,
23
,
SPI_SRAM_ADDR_BITLEN_S
)
;
//write address for cache command.
esp_psram_impl_quad.c:1094
SET_PERI_REG_MASK
(
SPI_CACHE_SCTRL_REG
(
0
)
,
SPI_USR_RD_SRAM_DUMMY_M
)
;
//enable cache read dummy
esp_psram_impl_quad.c:1095
SET_PERI_REG_BITS
(
SPI_CACHE_SCTRL_REG
(
0
)
,
SPI_SRAM_DUMMY_CYCLELEN_V
,
PSRAM_FAST_READ_QUAD_DUMMY
+
extra_dummy
,
esp_psram_impl_quad.c:1106
SET_PERI_REG_BITS
(
SPI_CACHE_SCTRL_REG
(
0
)
,
SPI_SRAM_DUMMY_CYCLELEN_V
,
PSRAM_FAST_READ_QUAD_DUMMY
+
extra_dummy
,
esp_psram_impl_quad.c:1124
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