READ_PERI_REG - syntax, references, description

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Code

Location

#define READ_PERI_REG(addr) ({ \

soc.h:107

uint32_t modebit = READ_PERI_REG(SPI_CTRL_REG(0));

bootloader_flash_config_esp32.c:138

uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;

clk_tree_ll.h:822

uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);

clk_tree_ll.h:841

uint32_t apb_freq_hz = (READ_PERI_REG(RTC_APB_FREQ_REG) & UINT16_MAX) << 12;

clk_tree_ll.h:875

uint32_t mode_backup = (READ_PERI_REG(SPI_USER_REG(spi_num)) >> SPI_FWRITE_DUAL_S) & 0xf;

esp_psram_impl_quad.c:302

uint32_t rd_mode_backup = READ_PERI_REG(SPI_CTRL_REG(spi_num)) & (SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M | SPI_FREAD_QUAD_M | SPI_FREAD_QIO_M);

esp_psram_impl_quad.c:303

while (READ_PERI_REG(SPI_EXT2_REG(0)) != 0);

esp_psram_impl_quad.c:313

while ((READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR));

esp_psram_impl_quad.c:318

*pRxData++ = READ_PERI_REG(SPI_W0_REG(spi_num) + (idx << 2));

esp_psram_impl_quad.c:334

while (READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR);

esp_psram_impl_quad.c:346

backup_usr[spi_num] = READ_PERI_REG(SPI_USER_REG(spi_num));

esp_psram_impl_quad.c:347

backup_usr1[spi_num] = READ_PERI_REG(SPI_USER1_REG(spi_num));

esp_psram_impl_quad.c:348

backup_usr2[spi_num] = READ_PERI_REG(SPI_USER2_REG(spi_num));

esp_psram_impl_quad.c:349

while (READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR);

esp_psram_impl_quad.c:415

uint32_t rd_mode_reg = READ_PERI_REG(SPI_CTRL_REG(0));

esp_psram_impl_quad.c:739

spi_status = READ_PERI_REG(SPI_EXT2_REG(PSRAM_SPI_NUM));

esp_psram_impl_quad.c:1021

while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {

esp_rom_spiflash.c:120

while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {

esp_rom_spiflash.c:142

while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {

esp_rom_spiflash.c:158

while ( READ_PERI_REG(PERIPHS_SPI_FLASH_CMD ) != 0 ) {

esp_rom_spiflash.c:213

while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {

esp_rom_spiflash.c:230

status_value = READ_PERI_REG(PERIPHS_SPI_FLASH_STATUS) & (spi->status_mask);

esp_rom_spiflash.c:233

while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {

esp_rom_spiflash.c:261

*addr_dest++ = READ_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4);

esp_rom_spiflash.c:297

*addr_dest++ = READ_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4);

esp_rom_spiflash.c:311

while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {

esp_rom_spiflash.c:328

modebit = READ_PERI_REG(PERIPHS_SPI_FLASH_CTRL);

esp_rom_spiflash.c:561

while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {

esp_rom_spiflash.c:691

uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);

rtc_cntl_ll.h:103

t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;

rtc_cntl_ll.h:104

return READ_PERI_REG(RTC_CNTL_WDTWPROTECT_REG) != RTC_CNTL_WDT_WKEY_VALUE;

rtc_wdt.c:16

time_tick = READ_PERI_REG(get_addr_reg(stage));

rtc_wdt.c:111

WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \

soc.h:121

WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \

soc.h:127

(READ_PERI_REG(reg) & (mask)); \

soc.h:133

WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \

soc.h:145

((READ_PERI_REG(reg)>>(shift))&(mask)); \

soc.h:151

status = READ_PERI_REG(UART_STATUS_REG(uart_no));

uart.h:263

buf[i] = READ_PERI_REG(fifo_addr);

uart_ll.h:323

READ_PERI_REG(fifo_addr);

uart_ll.h:366

READ_PERI_REG macro

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