I2S_PDM_TX_CLK_DAC_DEFAULT_CONFIG macro
I2S default PDM TX clock configuration for DAC line mode
Syntax
#define I2S_PDM_TX_CLK_DAC_DEFAULT_CONFIG(rate) { \
.sample_rate_hz = rate, \
.clk_src = I2S_CLK_SRC_DEFAULT, \
.mclk_multiple = I2S_MCLK_MULTIPLE_256, \
.up_sample_fp = 960, \
.up_sample_fs = (rate) / 100, \
.bclk_div = 13, \
}
Arguments
rate
sample rate (not suggest to exceed 48000 Hz, otherwise more glitches and noise may appear)
Notes
TX PDM can only be set to the following two up-sampling rate configurations: 1: fp = 960, fs = sample_rate_hz / 100, in this case, Fpdm = 128*48000 2: fp = 960, fs = 480, in this case, Fpdm = 128*Fpcm = 128*sample_rate_hz If the PDM receiver do not care the PDM serial clock, it's recommended set Fpdm = 128*48000. Otherwise, the second configuration should be adopted. The noise might be different with different configurations, this macro provides a set of configurations that have relatively high SNR (Signal Noise Ratio), you can also adjust them to fit your case.