HAL_ASSERT - syntax, references, description

References

Code

Location

#define HAL_ASSERT(__e) (__builtin_expect(!!(__e), 1) ? (void)0 : abort())

#define HAL_ASSERT(__e) (__builtin_expect(!!(__e), 1) ? (void)0 : __assert_func(__FILE__, __LINE__, __ASSERT_FUNC, #__e))

assert.h:39

HAL_ASSERT(((uint32_t)data_buf % 4) == 0);

adc_hal.c:200

HAL_ASSERT((per_eof_size % 4) == 0);

adc_hal.c:201

HAL_ASSERT(hal->cur_desc_ptr);

adc_hal.c:233

HAL_ASSERT(false);

adc_ll.h:376

HAL_ASSERT(false);

adc_ll.h:466

HAL_ASSERT(cache_level <= CACHE_LL_LEVEL_NUMS);

cache_hal_esp32.c:63

HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);

cache_ll.h:36

HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);

cache_ll.h:76

HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);

cache_ll.h:103

HAL_ASSERT(false); //out of range

cache_ll.h:108

HAL_ASSERT(vaddr_end < SOC_DRAM1_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h`

cache_ll.h:119

HAL_ASSERT(vaddr_end < SOC_DROM0_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h`

cache_ll.h:122

HAL_ASSERT(false);

cache_ll.h:125

HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);

cache_ll.h:144

HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);

cache_ll.h:179

HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);

cache_ll.h:211

HAL_ASSERT(false);

clk_tree_hal.c:29

HAL_ASSERT(false);

clk_tree_hal.c:84

HAL_ASSERT(divider > 0);

clk_tree_ll.h:637

HAL_ASSERT(divider > 0);

clk_tree_ll.h:794

HAL_ASSERT(false);

color_hal.c:39

HAL_ASSERT(clk_info->max_fract > 2);

hal_utils.c:26

HAL_ASSERT(clk_info->max_fract > 2);

hal_utils.c:71

HAL_ASSERT(bus_cfg->scl_low > 0);

i2c_ll.h:109

HAL_ASSERT(scl_high > 13);

i2c_ll.h:118

HAL_ASSERT(hw->scl_filter_cfg.thres <= 7);

i2c_ll.h:123

HAL_ASSERT(range == 0);

ledc_hal_iram.c:45

HAL_ASSERT(prescale <= 256 && prescale > 0);

mcpwm_ll.h:149

HAL_ASSERT(prescale <= 256 && prescale > 0);

HAL_ASSERT(false);

HAL_ASSERT(false);

HAL_ASSERT(false);

HAL_ASSERT(false);

HAL_ASSERT(prescale > 0 && prescale <= 16);

mcpwm_ll.h:1210

HAL_ASSERT(pulse_width >= 1);

mcpwm_ll.h:1259

HAL_ASSERT(prescale > 0);

mcpwm_ll.h:1615

HAL_ASSERT(shift_code);

mmu_hal.c:56

HAL_ASSERT(shift_code);

mmu_hal.c:76

HAL_ASSERT(vaddr % page_size_in_bytes == 0);

mmu_hal.c:84

HAL_ASSERT(paddr % page_size_in_bytes == 0);

mmu_hal.c:85

HAL_ASSERT(mmu_ll_check_valid_paddr_region(mmu_id, paddr, len));

mmu_hal.c:86

HAL_ASSERT(mmu_hal_check_valid_ext_vaddr_region(mmu_id, vaddr, len, MMU_VADDR_DATA | MMU_VADDR_INSTRUCTION));

mmu_hal.c:87

HAL_ASSERT(vaddr % page_size_in_bytes == 0);

mmu_hal.c:108

HAL_ASSERT(mmu_hal_check_valid_ext_vaddr_region(mmu_id, vaddr, len, MMU_VADDR_DATA | MMU_VADDR_INSTRUCTION));

mmu_hal.c:109

HAL_ASSERT(mmu_hal_check_valid_ext_vaddr_region(mmu_id, vaddr, 1, MMU_VADDR_DATA | MMU_VADDR_INSTRUCTION));

mmu_hal.c:123

HAL_ASSERT(mmu_ll_check_valid_paddr_region(mmu_id, paddr, 1));

HAL_ASSERT(false);

HAL_ASSERT(false);

HAL_ASSERT(false);

HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);

mmu_ll.h:274

HAL_ASSERT(false);

mmu_ll.h:284

HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);

mmu_ll.h:313

HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);

mmu_ll.h:332

HAL_ASSERT(mmu_ll_check_entry_valid(mmu_id, entry_id));

mmu_ll.h:333

HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);

mmu_ll.h:349

HAL_ASSERT(false);

mmu_ll.h:457

HAL_ASSERT(n >= num_words);

mpi_ll.h:168

HAL_ASSERT(false && "unsupported WDT stage");

mwdt_ll.h:122

HAL_ASSERT(false && "unsupported WDT stage");

mwdt_ll.h:149

HAL_ASSERT(clk_src == MWDT_CLK_SRC_APB);

mwdt_ll.h:289

HAL_ASSERT(false && "unsupported RMT clock source");

rmt_ll.h:155

HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range");

rmt_ll.h:200

HAL_ASSERT(high_ticks >= 1 && high_ticks <= 65536 && low_ticks >= 1 && low_ticks <= 65536 && "out of range high/low ticks");

rmt_ll.h:309

HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range");

rmt_ll.h:371

HAL_ASSERT((io_mask & mode_mask) == io_mask || (io_mask & mode_mask) == 0);

rtc_cntl_ll.h:38

HAL_ASSERT(buf->free_ptr == buf->read_ptr); //must return before recv again

sdio_slave_hal.c:101

HAL_ASSERT(sdio_ringbuf_offset_ptr(buf, RINGBUF_FREE_PTR, SDIO_SLAVE_SEND_DESC_SIZE) == ptr);

sdio_slave_hal.c:124

HAL_ASSERT(count * SDIO_SLAVE_SEND_DESC_SIZE==size);

sdio_slave_hal.c:127

HAL_ASSERT(rcv_res == ESP_OK);

sdio_slave_hal.c:193

HAL_ASSERT(rcv_res == ESP_OK);

sdio_slave_hal.c:205

HAL_ASSERT(first == last); //there should be only one desc remain

sdio_slave_hal.c:206

HAL_ASSERT(start_desc != NULL && end_desc != NULL);

sdio_slave_hal.c:314

HAL_ASSERT(send_get_state(hal) == STATE_SENDING);

sdio_slave_hal.c:356

HAL_ASSERT(hal->returned_desc == NULL);

sdio_slave_hal.c:397

HAL_ASSERT(hal->in_flight_end != NULL);

sdio_slave_hal.c:409

HAL_ASSERT(head == tail);

sdio_slave_hal.c:432

HAL_ASSERT(hal->in_flight_head != NULL);

sdio_slave_hal.c:449

HAL_ASSERT(send_get_state(hal) == STATE_GETTING_RESULT);

sdio_slave_hal.c:451

HAL_ASSERT(desc != NULL && desc->owner == 0);

sdio_slave_hal.c:637

HAL_ASSERT(prescale && prescale <= SDM_LL_PRESCALE_MAX);

sdm_ll.h:55

HAL_ASSERT(div > 1 && div <= 16);

sdmmc_ll.h:158

HAL_ASSERT(false);

sdmmc_ll.h:236

HAL_ASSERT(hw->clksrc.card0 == 0);

sdmmc_ll.h:253

HAL_ASSERT(hw->clksrc.card1 == 1);

sdmmc_ll.h:256

HAL_ASSERT(false);

sdmmc_ll.h:259

HAL_ASSERT(false);

sdmmc_ll.h:570

HAL_ASSERT(spi_ll_get_running_cmd(hw) == 0);

spi_hal_iram.c:45

default: HAL_ASSERT(false);

spi_ll.h:79

default: HAL_ASSERT(false);

spi_ll.h:93

default: HAL_ASSERT(false);

HAL_ASSERT(false);

HAL_ASSERT(false);

HAL_ASSERT(false);

HAL_ASSERT(false && "unsupported clock source");

timer_ll.h:89

HAL_ASSERT(divider >= 2 && divider <= 65536);

timer_ll.h:135

HAL_ASSERT(clk_src == TWAI_CLK_SRC_APB);

twai_ll.h:216

HAL_ASSERT macro

Syntax

Arguments

Examples

References

Call Tree

Data Use

Class Tree

Override Tree

Implementations

Instances

Lifecycle