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SourceVuESP-IDF Framework and ExamplesESP-IDFDPORT_APP_CACHE_CTRL1_REG

DPORT_APP_CACHE_CTRL1_REG macro

Syntax

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Summary

Declaration

from dport_reg.h:494

#define DPORT_APP_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x05C)

References

Code

Location

#define DPORT_APP_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x05C)

dport_reg.h:494

DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask);

uint32_t bus_mask= DPORT_REG_READ(DPORT_APP_CACHE_CTRL1_REG);

DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask);

DPORT_REG_SET_FIELD(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_SRAM_PAGE_MODE, mask_s);

cache_sram_mmu.c:119

DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);

cpu_start.c:355

DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);

cpu_start.c:357

DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1);

esp_psram.c:125

DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1 | DPORT_APP_CACHE_MASK_OPSDRAM); //use Dram1 to visit ext sram.

esp_psram_impl_quad.c:1143

DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_SRAM_PAGE_MODE, 0, DPORT_APP_CMMU_SRAM_PAGE_MODE_S);

esp_psram_impl_quad.c:1145

DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_FORCE_ON);