/* * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 *//* ... */#include"freertos/FreeRTOS.h"#include"esp_attr.h"#include"esp_private/periph_ctrl.h"#include"soc/soc_caps.h"#ifdef__PERIPH_CTRL_ALLOW_LEGACY_API#include"hal/clk_gate_ll.h"#endif#ifSOC_MODEM_CLOCK_IS_INDEPENDENT&&SOC_MODEM_CLOCK_SUPPORTED#include"esp_private/esp_modem_clock.h"#endif/// @brief For simplicity and backward compatible, we are using the same spin lock for both bus clock on/off and reset/// @note We may want to split them into two spin locks in the futurestaticportMUX_TYPEperiph_spinlock=portMUX_INITIALIZER_UNLOCKED;staticuint8_tref_counts[PERIPH_MODULE_MAX]={0};IRAM_ATTRvoidperiph_rcc_enter(void){portENTER_CRITICAL_SAFE(&periph_spinlock);}{ ... }IRAM_ATTRvoidperiph_rcc_exit(void){portEXIT_CRITICAL_SAFE(&periph_spinlock);}{ ... }uint8_tperiph_rcc_acquire_enter(periph_module_tperiph){periph_rcc_enter();returnref_counts[periph];}{ ... }voidperiph_rcc_acquire_exit(periph_module_tperiph,uint8_tref_count){ref_counts[periph]=++ref_count;periph_rcc_exit();}{ ... }uint8_tperiph_rcc_release_enter(periph_module_tperiph){periph_rcc_enter();returnref_counts[periph]-1;}{ ... }voidperiph_rcc_release_exit(periph_module_tperiph,uint8_tref_count){ref_counts[periph]=ref_count;periph_rcc_exit();}{ ... }voidperiph_module_enable(periph_module_tperiph){#ifdef__PERIPH_CTRL_ALLOW_LEGACY_APIassert(periph<PERIPH_MODULE_MAX);portENTER_CRITICAL_SAFE(&periph_spinlock);if(ref_counts[periph]==0){periph_ll_enable_clk_clear_rst(periph);}{...}ref_counts[periph]++;portEXIT_CRITICAL_SAFE(&periph_spinlock);/* ... */#endif}{ ... }voidperiph_module_disable(periph_module_tperiph){#ifdef__PERIPH_CTRL_ALLOW_LEGACY_APIassert(periph<PERIPH_MODULE_MAX);portENTER_CRITICAL_SAFE(&periph_spinlock);ref_counts[periph]--;if(ref_counts[periph]==0){periph_ll_disable_clk_set_rst(periph);}{...}portEXIT_CRITICAL_SAFE(&periph_spinlock);/* ... */#endif}{ ... }voidperiph_module_reset(periph_module_tperiph){#ifdef__PERIPH_CTRL_ALLOW_LEGACY_APIassert(periph<PERIPH_MODULE_MAX);portENTER_CRITICAL_SAFE(&periph_spinlock);periph_ll_reset(periph);portEXIT_CRITICAL_SAFE(&periph_spinlock);/* ... */#endif}{ ... }#if!SOC_IEEE802154_BLE_ONLY#ifSOC_BT_SUPPORTED||SOC_WIFI_SUPPORTED||SOC_IEEE802154_SUPPORTEDIRAM_ATTRvoidwifi_bt_common_module_enable(void){#ifSOC_MODEM_CLOCK_IS_INDEPENDENTmodem_clock_module_enable(PERIPH_PHY_MODULE);#elseportENTER_CRITICAL_SAFE(&periph_spinlock);if(ref_counts[PERIPH_WIFI_BT_COMMON_MODULE]==0){periph_ll_wifi_bt_module_enable_clk();}{...}ref_counts[PERIPH_WIFI_BT_COMMON_MODULE]++;portEXIT_CRITICAL_SAFE(&periph_spinlock);/* ... */#endif}{ ... }IRAM_ATTRvoidwifi_bt_common_module_disable(void){#ifSOC_MODEM_CLOCK_IS_INDEPENDENTmodem_clock_module_disable(PERIPH_PHY_MODULE);#elseportENTER_CRITICAL_SAFE(&periph_spinlock);ref_counts[PERIPH_WIFI_BT_COMMON_MODULE]--;if(ref_counts[PERIPH_WIFI_BT_COMMON_MODULE]==0){periph_ll_wifi_bt_module_disable_clk();}{...}portEXIT_CRITICAL_SAFE(&periph_spinlock);/* ... */#endif}{ ... }#endif/* ... *///#if SOC_BT_SUPPORTED || SOC_WIFI_SUPPORTED/* ... */#endif//#if !SOC_IEEE802154_BLE_ONLY#ifCONFIG_ESP_WIFI_ENABLEDvoidwifi_module_enable(void){#ifSOC_MODEM_CLOCK_IS_INDEPENDENTmodem_clock_module_enable(PERIPH_WIFI_MODULE);#elseportENTER_CRITICAL_SAFE(&periph_spinlock);periph_ll_wifi_module_enable_clk_clear_rst();portEXIT_CRITICAL_SAFE(&periph_spinlock);/* ... */#endif}{ ... }voidwifi_module_disable(void){#ifSOC_MODEM_CLOCK_IS_INDEPENDENTmodem_clock_module_disable(PERIPH_WIFI_MODULE);#elseportENTER_CRITICAL_SAFE(&periph_spinlock);periph_ll_wifi_module_disable_clk_set_rst();portEXIT_CRITICAL_SAFE(&periph_spinlock);/* ... */#endif}{ ... }#endif/* ... */// CONFIG_ESP_WIFI_ENABLED
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