reg::arch_info field

struct arc_reg_desc *arc_reg = reg->arch_info;

arc.c:887

struct arc_reg_desc *arc_reg = reg->arch_info;

arc.c:914

struct arc_reg_desc *arc_reg = reg->arch_info;

arc.c:929

arm_dpm_write_dirty_registers()

struct arc_reg_desc *arc_reg = reg->arch_info;

arc.c:1202

arc_restore_context()

struct arc_reg_desc *arc_reg = reg->arch_info;

arc.c:1213

arc_restore_context()

reg_arch_info = reg->arch_info;

arm7_9_common.c:1539

arm7_9_restore_context()

reg_arch_info = reg->arch_info;

arm7_9_common.c:1595

arm7_9_restore_context()

struct arm_reg *areg = r->arch_info;

arm7_9_common.c:1995

arm7_9_read_core_reg()

struct arm_reg *areg = r->arch_info;

arm7_9_common.c:2050

arm7_9_write_core_reg()

arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;

arm7_9_common.c:2543

arm7_9_dcc_completion()

r = cache->reg_list[i].arch_info;

arm_dpm.c:555

r = cache->reg_list[i].arch_info;

arm_dpm.c:803

arm_dpm_full_context()

struct arm_reg *reg_arch_info = reg->arch_info;

armv4_5.c:577

armv4_5_get_core_reg()

struct arm_reg *reg_arch_info = reg->arch_info;

armv4_5.c:597

armv4_5_set_core_reg()

reg_list[i].arch_info = &reg_arch_info[i];

armv4_5.c:692

arm_build_reg_cache()

reg_list[i].arch_info = &reg_arch_info[i];

armv4_5.c:738

arm_build_reg_cache()

free(cache->reg_list[0].arch_info);

armv4_5.c:775

arm_free_reg_cache()

struct arm_reg *armv7m_reg = reg->arch_info;

armv7m.c:219

armv7m_get_core_reg()

struct arm_reg *armv7m_reg = reg->arch_info;

armv7m.c:233

armv7m_set_core_reg()

struct arm_reg *armv7m_core_reg = r->arch_info;

armv7m.c:352

armv7m_read_core_reg()

struct arm_reg *armv7m_core_reg = r->arch_info;

armv7m.c:424

armv7m_write_core_reg()

reg_list[i].arch_info = &arch_info[i];

armv7m.c:795

armv7m_build_reg_cache()

free(cache->reg_list[0].arch_info);

armv7m.c:846

armv7m_free_reg_cache()

struct arm_reg *armv8_reg = reg->arch_info;

armv8.c:1680

armv8_get_core_reg()

struct arm_reg *armv8_reg = reg->arch_info;

armv8.c:1692

armv8_set_core_reg()

struct arm_reg *armv8_reg = reg->arch_info;

armv8.c:1727

armv8_get_core_reg32()

struct arm_reg *armv8_reg = reg->arch_info;

armv8.c:1753

armv8_set_core_reg32()

reg_list[i].arch_info = &arch_info[i];

armv8.c:1818

armv8_build_reg_cache()

reg_list32[i].arch_info = &arch_info[armv8_regs32[i].id];

armv8.c:1860

armv8_build_reg_cache()

free(cache->reg_list[0].arch_info);

armv8.c:1911

armv8_free_cache()

arm_reg = r->arch_info;

armv8_dpm.c:797

armv8_dpm_read_current_registers()

r = cache->reg_list[i].arch_info;

armv8_dpm.c:940

armv8_dpm_write_dirty_registers()

r = cache->reg_list[i].arch_info;

armv8_dpm.c:1056

armv8_dpm_full_context()

struct avr32_core_reg *avr32_reg = reg->arch_info;

avr32_ap7k.c:130

avr32_get_core_reg()

struct avr32_core_reg *avr32_reg = reg->arch_info;

avr32_ap7k.c:143

avr32_set_core_reg()

reg_list[i].arch_info = &arch_info[i];

avr32_ap7k.c:191

avr32_build_reg_cache()

struct dwt_reg_state *state = reg->arch_info;

cortex_m.c:2525

cortex_m_dwt_get_reg()

struct dwt_reg_state *state = reg->arch_info;

cortex_m.c:2538

cortex_m_dwt_set_reg()

r->arch_info = state;

cortex_m.c:2601

cortex_m_dwt_addreg()

free(cache->reg_list[i].arch_info);

cortex_m.c:2692

cortex_m_dwt_free()

struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info;

dsp563xx.c:400

dsp563xx_get_core_reg()

struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info;

dsp563xx.c:416

dsp563xx_set_core_reg()

reg_list[i].arch_info = &arch_info[i];

dsp563xx.c:469

dsp563xx_build_reg_cache()

arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].arch_info;

dsp563xx.c:606

dsp563xx_reg_ssh_read()

arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].arch_info;

dsp563xx.c:666

dsp563xx_reg_ssh_write()

arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSL].arch_info;

dsp563xx.c:708

dsp563xx_reg_ssl_read()

arch_info = dsp563xx->core_cache->reg_list[num].arch_info;

dsp563xx.c:741

dsp563xx_read_register()

arch_info = dsp563xx->core_cache->reg_list[num].arch_info;

dsp563xx.c:791

dsp563xx_write_register()

arch_info = dsp563xx->core_cache->reg_list[i].arch_info;

dsp563xx.c:873

dsp563xx_invalidate_x_context()

arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].arch_info;

dsp563xx.c:963

arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].arch_info;

dsp563xx.c:995

arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].arch_info;

dsp563xx.c:1003

arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].arch_info;

dsp563xx.c:1011

arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].arch_info;

dsp563xx.c:1019

embeddedice_build_reg_cache()

reg_list[i].arch_info = &arch_info[i];

embeddedice.c:200

free(reg_cache->reg_list[0].arch_info);

embeddedice.c:306

embeddedice_free_reg_cache()

struct embeddedice_reg *ice_reg = reg->arch_info;

embeddedice.c:345

embeddedice_read_reg_w_check()

struct embeddedice_reg *ice_reg = reg->arch_info;

embeddedice.c:503

embeddedice_write_reg()

struct esirisc_reg *reg_info = reg->arch_info;

esirisc.c:288

esirisc_save_context()

struct esirisc_reg *reg_info = reg->arch_info;

esirisc.c:305

esirisc_restore_context()

struct esirisc_reg *reg_info = reg->arch_info;

esirisc.c:1299

esirisc_read_reg()

struct esirisc_reg *reg_info = reg->arch_info;

esirisc.c:1322

esirisc_write_reg()

struct esirisc_reg *reg_info = reg->arch_info;

esirisc.c:1344

esirisc_read_csr()

struct esirisc_reg *reg_info = reg->arch_info;

esirisc.c:1367

esirisc_write_csr()

struct esirisc_reg *reg_info = reg->arch_info;

esirisc.c:1389

esirisc_get_reg()

struct esirisc_reg *reg_info = reg->arch_info;

esirisc.c:1403

esirisc_set_reg()

reg->arch_info = reg_info;

esirisc.c:1460

esirisc_build_reg_cache()

reg->arch_info = reg_info;

esirisc.c:1481

esirisc_build_reg_cache()

free(reg->arch_info);

esirisc.c:1498

esirisc_free_reg_cache()

free(reg->arch_info);

esirisc.c:1506

esirisc_free_reg_cache()

reg_list[i].arch_info = &arch_info[i];

etb.c:138

etb_build_reg_cache()

struct etb_reg *etb_reg = reg->arch_info;

etb.c:205

etb_read_reg_w_check()

struct etb_reg *etb_reg = reg->arch_info;

etb.c:286

etb_write_reg()

struct etm_reg *reg = cache->reg_list[i].arch_info;

etm.c:229

etm_reg_lookup()

reg->arch_info = ereg;

etm.c:267

etm_reg_add()

struct etm_reg *etm_reg = reg->arch_info;

etm.c:489

etm_read_reg_w_check()

struct etm_reg *etm_reg = reg->arch_info;

etm.c:577

etm_write_reg()

struct lakemont_core_reg *lakemont_reg = reg->arch_info;

lakemont.c:331

lakemont_get_core_reg()

struct lakemont_core_reg *lakemont_reg = reg->arch_info;

lakemont.c:342

lakemont_set_core_reg()

reg_list[i].arch_info = &arch_info[i];

lakemont.c:400

lakemont_build_reg_cache()

x86_32->pm_regs[I(EFLAGS)] = eflags & ~(EFLAGS_VM86 | EFLAGS_IF);

lakemont.c:514

if (write_hw_reg(t, EFLAGS, x86_32->pm_regs[I(EFLAGS)], 0) != ERROR_OK)

lakemont.c:515

x86_32->pm_regs[I(EFLAGS)],

lakemont.c:518

x86_32->pm_regs[I(EFLAGS)] & EFLAGS_VM86 ? 1 : 0,

lakemont.c:519

x86_32->pm_regs[I(EFLAGS)] & EFLAGS_IF ? 1 : 0);

lakemont.c:520

x86_32->pm_regs[I(CSAR)] = csar & ~CSAR_DPL;

lakemont.c:525

if (write_hw_reg(t, CSAR, x86_32->pm_regs[I(CSAR)], 0) != ERROR_OK)

lakemont.c:526

LOG_DEBUG("write CSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(CSAR)]);

lakemont.c:528

x86_32->pm_regs[I(SSAR)] = ssar & ~SSAR_DPL;

lakemont.c:531

if (write_hw_reg(t, SSAR, x86_32->pm_regs[I(SSAR)], 0) != ERROR_OK)

lakemont.c:532

LOG_DEBUG("write SSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(SSAR)]);

lakemont.c:534

x86_32->pm_regs[I(CR0)] = cr0 & ~CR0_PG;

lakemont.c:541

if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)

lakemont.c:542

LOG_DEBUG("cleared paging CR0_PG = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);

lakemont.c:544

x86_32->pm_regs[I(CR0)] =

lakemont.c:548

x86_32->pm_regs[I(CR0)] | (CR0_CD | CR0_NW | CR0_PG);

lakemont.c:549

if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)

lakemont.c:550

LOG_DEBUG("set CD, NW and PG, CR0 = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);

lakemont.c:552

access_register_command()

arch_info = x86_32->cache->reg_list[reg].arch_info;

lakemont.c:640

read_hw_reg()

arch_info = x86_32->cache->reg_list[reg].arch_info;

lakemont.c:674

write_hw_reg()

if (x86_32->pm_regs[I(CR0)] & CR0_PG)

lakemont.c:710

is_paging_enabled()

x86_32->pm_regs[I(CR0)] = x86_32->pm_regs[I(CR0)] & ~CR0_PG;

lakemont.c:725

disable_paging()

int err = x86_32->write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0);

lakemont.c:726

disable_paging()

x86_32->pm_regs[I(CR0)] = (x86_32->pm_regs[I(CR0)] | CR0_PG);

lakemont.c:737

enable_paging()

int err = x86_32->write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0);

lakemont.c:738

enable_paging()

struct mips32_core_reg *mips32_reg = reg->arch_info;

mips32.c:228

mips32_get_core_reg()

struct mips32_core_reg *mips32_reg = reg->arch_info;

mips32.c:242

mips32_set_core_reg()

reg_list[i].arch_info = &arch_info[i];

mips32.c:509

mips32_build_reg_cache()

struct mips64_core_reg *mips64_reg = reg->arch_info;

mips64.c:228

mips64_get_core_reg()

struct mips64_core_reg *mips64_reg = reg->arch_info;

mips64.c:242

mips64_set_core_reg()

r->arch_info = &arch_info[i];

mips64.c:406

mips64_build_reg_cache()

struct or1k_core_reg *or1k_reg = reg->arch_info;

or1k.c:453

or1k_get_core_reg()

struct or1k_core_reg *or1k_reg = reg->arch_info;

or1k.c:466

or1k_set_core_reg()

reg_list[i].arch_info = &arch_info[i];

or1k.c:536

or1k_build_reg_cache()

riscv_reg_info_t *reg_info = target->reg_cache->reg_list[number].arch_info;

riscv-013.c:880

free(target->reg_cache->reg_list[0].arch_info);

riscv.c:477

riscv_free_registers()

free(target->reg_cache->reg_list[i].arch_info);

riscv.c:480

riscv_free_registers()

riscv_reg_info_t *reg_info = reg->arch_info;

riscv.c:3699

register_get()

riscv_reg_info_t *reg_info = reg->arch_info;

riscv.c:3729

register_set()

r->arch_info = shared_reg_info;

riscv.c:3981

r->arch_info = calloc(1, sizeof(riscv_reg_info_t));

riscv.c:4383

if (!r->arch_info)

riscv.c:4384

((riscv_reg_info_t *) r->arch_info)->target = target;

riscv.c:4386

((riscv_reg_info_t *) r->arch_info)->custom_number = custom_number;

riscv.c:4387

dsp563xx_build_reg_cache()

struct stm8_core_reg *stm8_reg = reg->arch_info;

stm8.c:543

stm8_get_core_reg()

struct stm8_core_reg *stm8_reg = reg->arch_info;

stm8.c:557

stm8_set_core_reg()

reg_list[i].arch_info = &arch_info[i];

stm8.c:1219

stm8_build_reg_cache()

free(cache->reg_list[0].arch_info);

stm8.c:1266

stm8_free_reg_cache()

struct xscale_reg *arch_info = reg->arch_info;

xscale.c:2389

xscale_get_reg()

struct xscale_reg *arch_info = reg->arch_info;

xscale.c:2425

xscale_set_reg()

struct xscale_reg *dcsr_arch_info = dcsr->arch_info;

xscale.c:2462

xscale_write_dcsr_sw()

(*cache_p)->reg_list[i].arch_info = &arch_info[i];

xscale.c:2885

xscale_build_reg_cache()

free(cache->reg_list[0].arch_info);

xscale.c:2903

xscale_free_reg_cache()

struct xtensa *xtensa = (struct xtensa *)reg->arch_info;

xtensa.c:434

xtensa_core_reg_get()

struct xtensa *xtensa = (struct xtensa *)reg->arch_info;

xtensa.c:452

xtensa_core_reg_set()

reg_list[didx].arch_info = xtensa;

xtensa.c:2976

xtensa_build_reg_cache()

xtensa->empty_regs[i].arch_info = xtensa;

xtensa.c:3020

xtensa_build_reg_cache()

Call Tree

All items filtered out

Data Use

reg::arch_info is written by 19 functions and is read by 85 functions:

or1k_build_reg_cache()

arm_build_reg_cache()

armv7m_build_reg_cache()

armv8_build_reg_cache()

avr32_build_reg_cache()

cortex_m_dwt_addreg()

embeddedice_build_reg_cache()

etb_build_reg_cache()

etm_reg_add()

lakemont_build_reg_cache()

mips32_build_reg_cache()

xscale_build_reg_cache()

stm8_build_reg_cache()

esirisc_build_reg_cache()

mips64_build_reg_cache()

arc_init_reg()

xtensa_build_reg_cache()

reg::arch_info

or1k_get_core_reg()

or1k_set_core_reg()

arm7_9_restore_context()

arm7_9_read_core_reg()

arm7_9_write_core_reg()

arm7_9_dcc_completion()

armv4_5_get_core_reg()

armv4_5_set_core_reg()

arm_free_reg_cache()

armv7m_get_core_reg()

armv7m_set_core_reg()

armv7m_read_core_reg()

armv7m_write_core_reg()

armv7m_free_reg_cache()

armv8_get_core_reg()

armv8_set_core_reg()

armv8_get_core_reg32()

armv8_set_core_reg32()

armv8_free_cache()

armv8_dpm_read_current_registers()

armv8_dpm_write_dirty_registers()

armv8_dpm_full_context()

arm_dpm_write_dirty_registers()

arm_dpm_full_context()

avr32_get_core_reg()

avr32_set_core_reg()

cortex_m_dwt_get_reg()

cortex_m_dwt_set_reg()

cortex_m_dwt_free()

dsp563xx_get_core_reg()

dsp563xx_set_core_reg()

dsp563xx_reg_ssh_read()

dsp563xx_reg_ssh_write()

dsp563xx_reg_ssl_read()

dsp563xx_read_register()

dsp563xx_write_register()

dsp563xx_invalidate_x_context()

embeddedice_free_reg_cache()

embeddedice_read_reg_w_check()

embeddedice_write_reg()

etb_read_reg_w_check()

etb_write_reg()

etm_reg_lookup()

etm_read_reg_w_check()

etm_write_reg()

lakemont_get_core_reg()

lakemont_set_core_reg()

mips32_get_core_reg()

mips32_set_core_reg()

xscale_get_reg()

xscale_set_reg()

xscale_write_dcsr_sw()

xscale_free_reg_cache()

stm8_get_core_reg()

stm8_set_core_reg()

stm8_free_reg_cache()

riscv_free_registers()

register_get()

register_set()

access_register_command()

esirisc_save_context()

esirisc_restore_context()

esirisc_free_reg_cache()

mips64_get_core_reg()

mips64_set_core_reg()

arc_get_register()

arc_set_register()