/* SPDX-License-Identifier: GPL-2.0-or-later *//*************************************************************************** * Copyright (C) 2015 Oleksij Rempel * * linux@rempel-privat.de * ***************************************************************************//* ... */#ifndefOPENOCD_TARGET_ARM7A_CACHE_L2X_H#defineOPENOCD_TARGET_ARM7A_CACHE_L2X_H#defineL2X0_CACHE_LINE_SIZE32/* source: linux/arch/arm/include/asm/hardware/cache-l2x0.h */#defineL2X0_CACHE_ID0x000#defineL2X0_CACHE_TYPE0x004#defineL2X0_CTRL0x100#defineL2X0_AUX_CTRL0x104#defineL2X0_TAG_LATENCY_CTRL0x108#defineL2X0_DATA_LATENCY_CTRL0x10C#defineL2X0_EVENT_CNT_CTRL0x200#defineL2X0_EVENT_CNT1_CFG0x204#defineL2X0_EVENT_CNT0_CFG0x208#defineL2X0_EVENT_CNT1_VAL0x20C#defineL2X0_EVENT_CNT0_VAL0x210#defineL2X0_INTR_MASK0x214#defineL2X0_MASKED_INTR_STAT0x218#defineL2X0_RAW_INTR_STAT0x21C#defineL2X0_INTR_CLEAR0x220#defineL2X0_CACHE_SYNC0x730#defineL2X0_DUMMY_REG0x740#defineL2X0_INV_LINE_PA0x770#defineL2X0_INV_WAY0x77C#defineL2X0_CLEAN_LINE_PA0x7B0#defineL2X0_CLEAN_LINE_IDX0x7B8#defineL2X0_CLEAN_WAY0x7BC#defineL2X0_CLEAN_INV_LINE_PA0x7F0#defineL2X0_CLEAN_INV_LINE_IDX0x7F8#defineL2X0_CLEAN_INV_WAY0x7FC/* * The lockdown registers repeat 8 times for L310, the L210 has only one * D and one I lockdown register at 0x0900 and 0x0904. *//* ... */#defineL2X0_LOCKDOWN_WAY_D_BASE0x900#defineL2X0_LOCKDOWN_WAY_I_BASE0x904#defineL2X0_LOCKDOWN_STRIDE0x08#defineL2X0_ADDR_FILTER_START0xC00#defineL2X0_ADDR_FILTER_END0xC04#defineL2X0_TEST_OPERATION0xF00#defineL2X0_LINE_DATA0xF10#defineL2X0_LINE_TAG0xF30#defineL2X0_DEBUG_CTRL0xF40#defineL2X0_PREFETCH_CTRL0xF60#defineL2X0_POWER_CTRL0xF80#defineL2X0_DYNAMIC_CLK_GATING_EN(1<<1)#defineL2X0_STNDBY_MODE_EN(1<<0)/* Registers shifts and masks */#defineL2X0_CACHE_ID_PART_MASK(0xf<<6)#defineL2X0_CACHE_ID_PART_L210(1<<6)#defineL2X0_CACHE_ID_PART_L310(3<<6)#defineL2X0_CACHE_ID_RTL_MASK0x3f#defineL2X0_CACHE_ID_RTL_R0P00x0#defineL2X0_CACHE_ID_RTL_R1P00x2#defineL2X0_CACHE_ID_RTL_R2P00x4#defineL2X0_CACHE_ID_RTL_R3P00x5#defineL2X0_CACHE_ID_RTL_R3P10x6#defineL2X0_CACHE_ID_RTL_R3P20x8#defineL2X0_AUX_CTRL_MASK0xc0000fff#defineL2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT0#defineL2X0_AUX_CTRL_DATA_RD_LATENCY_MASK0x7#defineL2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT3#defineL2X0_AUX_CTRL_DATA_WR_LATENCY_MASK(0x7<<3)#defineL2X0_AUX_CTRL_TAG_LATENCY_SHIFT6#defineL2X0_AUX_CTRL_TAG_LATENCY_MASK(0x7<<6)#defineL2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT9#defineL2X0_AUX_CTRL_DIRTY_LATENCY_MASK(0x7<<9)#defineL2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT16#defineL2X0_AUX_CTRL_WAY_SIZE_SHIFT17#defineL2X0_AUX_CTRL_WAY_SIZE_MASK(0x7<<17)#defineL2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT22#defineL2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT26#defineL2X0_AUX_CTRL_NS_INT_CTRL_SHIFT27#defineL2X0_AUX_CTRL_DATA_PREFETCH_SHIFT28#defineL2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT29#defineL2X0_AUX_CTRL_EARLY_BRESP_SHIFT30#defineL2X0_LATENCY_CTRL_SETUP_SHIFT0#defineL2X0_LATENCY_CTRL_RD_SHIFT4#defineL2X0_LATENCY_CTRL_WR_SHIFT8#defineL2X0_ADDR_FILTER_EN1#defineL2X0_CTRL_EN1#defineL2X0_WAY_SIZE_SHIFT374 definesstructl2x0_regs{unsignedlongphy_base;unsignedlongaux_ctrl;/* * Whether the following registers need to be saved/restored * depends on platform *//* ... */unsignedlongtag_latency;unsignedlongdata_latency;unsignedlongfilter_start;unsignedlongfilter_end;unsignedlongprefetch_ctrl;unsignedlongpwr_ctrl;unsignedlongctrl;unsignedlongaux2_ctrl;...};structouter_cache_fns{void(*inv_range)(unsignedlong,unsignedlong);void(*clean_range)(unsignedlong,unsignedlong);void(*flush_range)(unsignedlong,unsignedlong);void(*flush_all)(void);void(*disable)(void);void(*resume)(void);/* This is an ARM L2C thing */void(*write_sec)(unsignedlong,unsigned);void(*configure)(conststructl2x0_regs*);...};structl2c_init_data{constchar*type;unsignedway_size_0;unsignednum_lock;void(*enable)(uint32_t,uint32_t,unsigned);void(*fixup)(uint32_t,uint32_t,structouter_cache_fns*);void(*save)(uint32_t);void(*configure)(uint32_t);structouter_cache_fnsouter_cache;...};externconststructcommand_registrationarm7a_l2x_cache_command_handler[];intarmv7a_l2x_cache_flush_virt(structtarget*target,target_addr_tvirt,uint32_tsize);intarm7a_l2x_flush_all_data(structtarget*target);/* ... */#endif/* OPENOCD_TARGET_ARM7A_CACHE_L2X_H */
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